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US20160372199 NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, MEMORY SYSTEM INCLUDING THE NON-VOLATILE MEMORY DEVICE, AND OPERATING METHOD OF THE MEMORY SYSTEM  
An operating method of a non-volatile memory device having a string including a plurality of memory cells and a plurality of auxiliary cells, the plurality of memory cells and the plurality of...
US20160372198 MEMORY DEVICE HAVING ONLY THE TOP POLY CUT  
Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array...
US20160343454 STRESS PATTERNS TO DETECT SHORTS IN THREE DIMENSIONAL NON-VOLATILE MEMORY  
A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns The managing...
US20160343450 3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF  
Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially...
US20160343446 APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES  
Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including...
US20160336339 DEVICE AND METHOD FOR DETERMINING ELECTRICAL CHARACTERISTICS FOR ELLIPSE GATE-ALL-AROUND FLASH MEMORY  
Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string...
US20160336073 ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH  
Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or...
US20160329101 THREE-DIMENSIONAL P-I-N MEMORY DEVICE AND METHOD READING THEREOF USING HOLE CURRENT DETECTION  
A p-i-n junction structure is formed within a memory film laterally surrounded by an alternating plurality of electrically insulating layers and electrically conductive layers to provide a...
US20160322373 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each...
US20160314840 THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE  
A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground...
US20160307914 THREE DIMENSIONAL NAND FLASH WITH SELF-ALIGNED SELECT GATE  
An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory...
US20160293584 Three-Dimensional Vertical Memory Comprising Dice with Different Interconnect Levels  
The present invention discloses a three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of...
US20160284726 MID-TUNNELING DIELECTRIC BAND GAP MODIFICATION FOR ENHANCED DATA RETENTION IN A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE  
A tunneling dielectric layer for a vertical memory device is formed with a stack that provides a barrier height profile for high data retention tolerance. Memory stack structures extend through a...
US20160284409 SEMICONDUCTOR MEMORY DEVICE HAVING A MEMORY STRING THAT INCLUDES A TRANSISTOR HAVING A CHARGE STORED THEREIN TO INDICATE THE MEMORY STRING IS DEFECTIVE  
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which...
US20160276032 SEMICONDUCTOR MEMORY DEVICE AND DATA ERASING METHOD  
A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the...
US20160267989 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF  
A nonvolatile semiconductor memory device, includes a memory cell array, and a control circuit configured to control voltage applied to the memory cell array. The memory cell array includes: a...
US20160267982 NAND String Utilizing Floating Body Memory Cell  
NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string...
US20160267981 SEMICONDUCTOR MEMORY DEVICE  
A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit...
US20160267980 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM  
A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth memory cell transistors; a first...
US20160260732 VERTICAL THIN-CHANNEL MEMORY  
A memory device which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the...
US20160260496 NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND METHODS OF OPERATING THE DEVICE AND SYSTEM  
Provided is a method of operating a non-volatile memory device including a plurality of strings, each string including a plurality of memory cells vertically stacked on a substrate. The method...
US20160254053 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
According to an embodiment, a nonvolatile semiconductor memory device comprises: a memory string including a plurality of memory cells connected in series; a first select gate transistor connected...
US20160247570 AND-TYPE SGVC ARCHITECTURE FOR 3D NAND FLASH  
A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in...
US20160232981 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME  
According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory...
US20160225451 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME  
A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first...
US20160217868 Pre-Program Detection Of Threshold Voltages Of Select Gate Transistors In A Memory Device  
A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate transistors is evaluated, such as in...
US20160217865 Method Of Reducing Hot Electron Injection Type Of Read Disturb In Dummy Memory Cells  
Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In...
US20160211027 OPERATING METHOD OF A NONVOLATILE MEMORY DEVICE  
A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first...
US20160211023 OPERATION MODES FOR AN INVERTED NAND ARCHITECTURE  
Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming...
US20160189778 TECHNIQUES FOR PROGRAMMING OF SELECT GATES IN NAND MEMORY  
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages,...
US20160189777 SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM  
A semiconductor storage device has a memory string including a memory cell, a bit line electrically connected to one end of the memory string, and a sense amplifier electrically connected to the...
US20160172040 MEMORY DEVICE AND DATA ERASING METHOD THEREOF  
A memory device comprises a first memory string and a second memory string. The first memory string is coupled to a first bit line and a plurality of word lines, and the second memory string is...
US20160163391 FLASH MEMORY AND PROGRAMMING METHOD THEREOF  
A programming method of an NAND flash memory is provided, for narrowing a distribution width of a threshold voltage. The method includes a step of verification reading for verifying a threshold...
US20160163389 THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE  
A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line...
US20160141039 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso,...
US20160133327 MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES  
Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second...
US20160125944 SEMICONDUCTOR DEVICE  
A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line...
US20160118133 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME  
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells...
US20160118122 VERTICAL STRUCTURE SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME  
A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate...
US20160111164 Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory  
Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device...
US20160104533 APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES  
Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A. plurality of word lines may be...
US20160099066 Bit Line Pre-Charge With Current Reduction  
Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel...
US20160099064 NON-VOLATILE SEMICONDUCTOR MEMORY WITH HIGH RELIABILITY AND DATA ERASING METHOD THEREOF  
A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An erasing method of a flash memory is...
US20160099059 NON-VOLATILE MEMORY AND METHOD WITH ADJUSTED TIMING FOR INDIVIDUAL PROGRAMMING PULSES  
A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a...
US20160099056 PAGE BUFFER CIRCUIT FOR NAND FLASH MEMORY  
A page buffer for a NAND flash memory array includes a pre-charge switch, a first switch, a read switch, a write switch, a latch, and a data switch. The pre-charge switch is coupled between a...
US20160093390 Read With Look-Back Combined With Programming With Asymmetric Boosting In Memory  
A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an...
US20160086675 WORD LINE DEPENDENT TEMPERATURE COMPENSATION SCHEME DURING SENSING TO COUNTERACT CROSS-TEMPERATURE EFFECT  
Methods for reducing cross-temperature dependent word line failures using a temperature dependent sensing scheme during a sensing operation are described. In some embodiments, during a read...
US20160086674 TEMPERATURE DEPENDENT SENSING SCHEME TO COUNTERACT CROSS-TEMPERATURE THRESHOLD VOLTAGE DISTRIBUTION WIDENING  
Methods for reducing cross-temperature threshold voltage distribution widening by applying a temperature dependent sensing scheme during read operations are described. In some embodiments, during...
US20160086671 Utilizing NAND Strings in Dummy Blocks for Faster Bit Line Precharge  
In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the...
US20160086666 MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE  
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory...