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US20100277984 NONVOLATILE SEMICONDUCTOR MEMORY  
In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read...
US20100271879 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
A semiconductor integrated circuit includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a...
US20100265770 NONVOLATILE SEMICONDUCTOR MEMORY  
A nonvolatile semiconductor memory comprising: a first semiconductor layer having a first stripe-shaped region and a second stripe-shaped region which is adjacent to the first stripe-shaped...
US20100259990 MEMORY ARRAYS, MEMORY DEVICES AND METHODS OF READING MEMORY CELLS  
Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to...
US20100254192 MEMORY WITH CORRELATED RESISTANCE  
Methods, systems, and devices are disclosed, such as a system for sequentially writing to a data locations coupled to one another in series. In certain embodiments, the system includes a plurality...
US20100238733 NAND FLASH MEMORY  
A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be...
US20100238732 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE  
When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal...
US20100238731 PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL  
A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a...
US20100214848 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME  
A nonvolatile memory device includes a first node, a current source configured to have a current value determined according to a voltage supplied to the first node, and a memory cell string...
US20100214840 MULTI-DOT FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME  
A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a...
US20100214839 NAND FLASH MEMORY STRING APPARATUS AND METHODS OF OPERATION THEREOF  
A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second...
US20100202216 NON-VOLATILE MEMORY DEVICE AND SYSTEM HAVING REDUCED BIT LINE BIAS TIME  
A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and...
US20100202207 ALL-BIT-LINE ERASE VERIFY AND SOFT PROGRAM VERIFY  
Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One...
US20100195406 METHOD OF OPERATING NONVOLATILE MEMORY DEVICE  
A method of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor, including...
US20100195396 SEMICONDUCTOR MEMORY DEVICE AND SELF-TEST METHOD OF THE SAME  
A semiconductor memory device includes a main memory includes a nonvolatile memory, and a buffer which stores input/output data of the nonvolatile memory, a buffer unit of the main memory, the...
US20100195395 Non-volatile memory device having vertical structure and method of operating the same  
A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first...
US20100195383 Isolated P-well Architecture for a Memory Device  
A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to...
US20100182843 CURRENT SENSING FOR FLASH  
A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing process that places a current source...
US20100177566 Non-volatile memory device having stacked structure, and memory card and electronic system including the same  
Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell...
US20100172182 Nonvolatile memory device and method for operating the same  
Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of...
US20100165733 NAND NONVOLATILE SEMICONDUCTOR MEMORY  
A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines...
US20100157677 NON-VOLATILE SEMICONDUCTOR MEMORY  
A non-volatile semiconductor memory device is provided so that chip size may not increase and occurrence of misreading induced by capacitance of adjacent global bit lines GBL may be prevented, and...
US20100153628 METHOD OF FABRICATING SYSTEMS INCLUDING HEAT-SENSITIVE MEMORY DEVICES  
A system code is stored in a first nonvolatile memory. The first nonvolatile memory and a second nonvolatile memory are heated during assembly of an electronic device including the first...
US20100142280 PROGRAMMING MEMORY DEVICES  
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is...
US20100128533 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
A nonvolatile memory device includes a plurality of strings each of which is configured with a first select transistor, a second select transistor, and a plurality of memory cells connected in...
US20100128525 ALL-BIT-LINE ERASE VERIFY AND SOFT PROGRAM VERIFY  
Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One...
US20100124118 Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array  
A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups...
US20100124116 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE  
Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a...
US20100115176 DATA TRANSFER AND PROGRAMMING IN A MEMORY DEVICE  
Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data...
US20100110792 PAIR BIT LINE PROGRAMMING TO IMPROVE BOOST VOLTAGE CLAMPING  
A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an...
US20100110789 MEMORY DEVICE BIASING METHOD AND APPARATUS  
Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example,...
US20100091566 NAND FLASH MEMORY  
In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source...
US20090116290 METHODS AND APPARATUSES RELATING TO AUTOMATIC CELL THRESHOLD VOLTAGE MEASUREMENT  
Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory...
US20080239818 THREE DIMENSIONAL NAND MEMORY  
A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of...
US20080205148 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality...
US20080106942 NAND TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a...
US20170186488 SEMICONDUCTOR MEMORY DEVICE  
A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit...
US20170178730 METHODS AND APPARATUSES INCLUDING A STRING OF MEMORY CELLS HAVING A FIRST SELECT TRANSISTOR COUPLED TO A SECOND SELECT TRANSISTOR  
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled...
US20170170187 GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE  
A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select...
US20170148517 THREE-DIMENSIONAL VERTICAL NOR FLASH THIN FILM TRANSISTOR STRINGS  
A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily...
US20170092362 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME NONVOLATILE SEMICONDUCTOR STORAGE DEVICE  
A nonvolatile semiconductor storage device a memory cell array including a plurality of memory cell units arranged in a matrix configuration, the memory cell units including a memory string...
US20170084345 NON-VOLATILE MEMORY WITH SUPPLEMENTAL SELECT GATES  
A non-volatile memory system includes a plurality of groups of connected non-volatile memory cells (e.g., charge trapping memory cells), a select line, and a plurality of select gates connected to...
US20170069394 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a memory cell, a word line electrically connected to a gate of the memory cell, and a source line electrically connected to a first end of the memory cell....
US20170069387 NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF CONTROLLING THE NONVOLATILE SEMICONDUCTOR MEMORY  
A nonvolatile semiconductor memory includes a memory cell array, the memory cell array including a memory string and a matrix of a plurality of memory cell units, the memory string containing a...
US20170062059 MEMORY DEVICE, MEMORY SYSTEM, METHOD OF OPERATING MEMORY DEVICE, AND METHOD OF OPERATING MEMORY SYSTEM  
A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines...
US20170053700 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution...
US20170047123 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD THEREOF  
Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory...
US20160379717 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading...
US20160372202 NON-VOLATILE MEMORY DEVICE HAVING MULTIPLE STRING SELECT LINES  
Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of...
US20160372200 FAST SCAN TO DETECT BIT LINE DISCHARGE TIME  
Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality...