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US20110310670 VERTICALLY-INTEGRATED NONVOLATILE MEMORY DEVICES HAVING LATERALLY-INTEGRATED GROUND SELECT TRANSISTORS  
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This...
US20100202206 NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND CHANNELS AND METHODS OF FORMING THE SAME  
A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower...
US20090285027 Non-volatile memory devices and methods of operating non-volatile memory devices  
A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile...
US20080285350 Circuit and method for a three dimensional non-volatile memory  
An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel...
US20080181007 Semiconductor Device with Reduced Structural Pitch and Method of Making the Same  
A method of manufacturing structures in a workpiece includes: providing a portion of a cover layer on a predetermined section of the workpiece, providing a resist layer over the workpiece and the...
US20150228342 Flash Memory Having Dual Supply Operation  
A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash...
US20140328126 Flash Memory Having Dual Supply Operation  
A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash...
US20140293703 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME  
A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first...
US20140241062 Modular, Scalable Rigid Flex Memory Module  
A memory card in a computer system includes a plurality of memory elements on a NAND flash board. The NAND flash board is connected to a controller board by a flexible connector. The flexible...
US20140133238 METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS  
A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a...
US20140133228 Key-Value Addressed Storage Drive Using NAND Flash Based Content Addressable Memory  
A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so...
US20140056077 COMPENSATING FOR OFF-CURRENT IN A MEMORY  
A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current...
US20140022847 NAND FLASH MEMORY PROGRAMMING  
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming...
US20130148427 Z-Direction Decoding for Three Dimensional Memory Array  
The switch transistors in the NAND strings have combinations of threshold voltage levels that vary across the levels of a three dimensional memory array. A bias arrangement is applied to the...
US20130088920 LOW VOLTAGE PROGRAMMING IN NAND FLASH WITH TWO STAGE SOURCE SIDE BIAS  
A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by...
US20130083601 VERTICAL NAND MEMORY  
A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND...
US20130044545 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME  
A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first...
US20130003459 Read Error Recovery for Solid-State Memory Based on Cumulative Background Charges  
A read error is determined that affects a page of solid-state, non-volatile memory. The page is associated with a selected word line that crosses a plurality of NAND strings coupled to respective...
US20120081962 LOW VOLTAGE PROGRAMMING IN NAND FLASH  
A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by...
US20110305089 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS  
According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to...
US20110280077 MULTI-SEMICONDUCTOR MATERIAL VERTICAL MEMORY STRINGS, STRINGS OF MEMORY CELLS HAVING INDIVIDUALLY BIASABLE CHANNEL REGIONS, MEMORY ARRAYS INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME  
Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such...
US20110134694 High Voltage Generation And Control In Source-Side Injection Programming Of Non-Volatile Memory  
Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to...
US20110090738 NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME  
A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory...
US20100195397 Controlled Boosting In Non-Volatile Memory Soft Programming  
A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block...
US20090257279 MEMORY DEVICE OPERATION  
Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory...
US20090086542 High Voltage Generation and Control in Source-Side Injection Programming of Non-Volatile Memory  
Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to...
US20090021982 SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF  
A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current...
US20080002469 Non-volatile memory  
Disclosed herein is a non-volatile memory, including: a memory cell array to be accessed with data including a data portion and a specific field as a unit of access; a buffer configured to hold...
US20150071000 SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE JUDGING METHOD THEREOF  
A semiconductor memory device is provided with a plurality of memory cells connected to a plurality of word lines, a word-line leakage detector configured to detect a leakage current generated on...
US20150070998 VREAD BIAS ALLOCATION ON WORD LINES FOR READ DISTURB REDUCTION IN 3D NON-VOLATILE MEMORY  
Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations...
US20150009756 SENSING OPERATIONS IN A MEMORY DEVICE  
Methods and apparatus for sensing operations in memory devices are disclosed. In at least one embodiment, a sensing operation to determine negative threshold voltages in memory cells by an...
US20140376313 APPARATUSES AND METHODS FOR LIMITING STRING CURRENT IN A MEMORY  
Apparatuses, current control circuits, and methods for limiting string current in a memory are described. An example apparatus includes a memory cell string including a memory cell. The example...
US20140362645 3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter  
A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the...
US20140362642 3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter  
A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the...
US20140313828 SHARING SUPPORT CIRCUITRY IN A MEMORY  
A memory device, system, and method for operation of a memory device are disclosed. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of...
US20140204674 LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME  
The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the...
US20140140130 SEMICONDUCTOR MEMORY DEVICE FOR AND METHOD OF APPLYING TEMPERATURE-COMPENSATED WORD LINE VOLTAGE DURING READ OPERATION  
A semiconductor memory device configured to apply a temperature-compensated word line voltage to a word line during a data read operation includes a memory cell array including a plurality of word...
US20140063961 WRITE DATA PRESERVATION FOR NON-VOLATILE STORAGE  
Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be...
US20130223150 APPARATUS AND METHODS FOR APPLYING A NON-ZERO VOLTAGE DIFFERENTIAL ACROSS A MEMORY CELL NOT INVOLVED IN AN ACCESS OPERATION  
Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics.
US20120140558 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A control circuit applies a write pulse voltage to a selected word line to perform a write operation to 1-page memory cells along the selected word line. The circuit then performs a verify read...
US20120020161 Multiple Plane, Non-Volatile Memory With Synchronized Control  
This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each...
US20110235422 APPARATUS HAVING A STRING OF MEMORY CELLS  
Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some...
US20110205796 NONVOLATILE MEMORY DEVICE AND SYSTEM PERFORMING REPAIR OPERATION FOR DEFECTIVE MEMORY CELL  
A nonvolatile memory device comprises a main memory cell array, a redundancy memory cell array, and a controller. The main memory cell array comprises a plurality of bit lines each connected to a...
US20110194350 COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE  
In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a...
US20110170352 NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES  
A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors....
US20110149654 NAND Programming Technique  
A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided...
US20110110159 Nonvolatile Memory Device for Preventing Program Disturbance and Method of Programming the Nonvolatile Memory Device  
A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least...
US20110110158 MASS STORAGE DEVICE WITH SOLID-STATE MEMORY COMPONENTS CAPABLE OF INCREASED ENDURANCE  
A mass storage device that utilizes one or more solid-state memory components to store data for a host system, and a method for increasing the write endurance of the memory components. The memory...
US20110096604 SEMICONDUCTOR MEMORY DEVICE INCLUDING ALTERNATELY ARRANGED CONTACT MEMBERS  
According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first...
US20110038211 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME  
A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors...