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US20090103365 Sensing of memory cells in NAND flash  
An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage...
US20090080258 ERASE METHOD IN THIN FILM NONVOLATILE MEMORY  
An erase method applicable to dual-gate memory strings has key advantages over erase methods for other thin-film non-volatile memory strings. The advantages include (a) fast erase without any...
US20080225594 Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array  
A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided...
US20150055413 THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY DEVICES WITH BURIED WORD LINE SELECTORS  
Three-dimensional NAND stacked memory devices are described that include a stack including alternating word line and dielectric layers and a plurality of NAND strings of memory cells formed in...
US20150043278 Group Word Line Erase And Erase-Verify Methods For 3D Non-Volatile Memory  
An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide...
US20130235667 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME  
A method is provided for programming a nonvolatile memory device, which includes multiple memory cells connected in series in a direction substantially perpendicular to a substrate. The method...
US20130170297 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME  
According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground...
US20130107626 METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES  
Methods for segmented programming, program verify, and memory devices are disclosed. One such method for programming includes biasing memory cells with a programming voltage and program verifying...
US20100315875 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME  
Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string,...
US20100277981 NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS  
Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell...
US20100067299 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other...
US20090238002 NAND TYPE NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF  
A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word...
US20090129165 Nonvolatile Memory Devices and Methods of Operating Same to Inhibit Parasitic Charge Accumulation Therein  
Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory...
US20080232169 NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES  
A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of...
US20140269078 MEMORY ARCHITECTURE OF THIN FILM 3D ARRAY  
A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the...
US20140241064 NONVOLATILE MEMORY AND OPERATING METHOD OF NONVOLATILE MEMORY  
An operating method of a nonvolatile memory is provided which includes adjusting a threshold voltage of at least one first memory cell adjacent to a substrate in each cell string to be higher than...
US20140104952 INTEGRATED CIRCUIT DEVICE  
A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is...
US20120206965 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, an erase verification execution unit that makes an erase verify operation of a memory cell, on which an erase operation is performed, to be performed, a...
US20120081964 SENSING FOR NAND MEMORY BASED ON WORD LINE POSITION  
In a NAND non-volatile memory system, a sensing process accounts for a relative position of a selected non-volatile storage element in a NAND string. In one approach, the storage elements are...
US20110188313 DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS  
Techniques for operating non-volatile storage compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group...
US20110103147 NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME  
A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective...
US20110096597 PROGRAMMING A FLASH MEMORY DEVICE  
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is...
US20080310232 ERASE VERIFY FOR MEMORY DEVICES  
Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to...
US20080259687 Integrated Circuits and Methods of Manufacturing Thereof  
Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a...
US20080074927 Memory array having an interconnect and method of manufacture  
A memory array includes first, second, third and forth memory cell strings. Each of the first, second, third, and fourth memory cell strings includes a number of serially-coupled memory cells,...
US20150063033 Selective Word Line Erase In 3D Non-Volatile Memory  
An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or...
US20140355351 CONTROLLER  
A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update...
US20140269081 SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS  
An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing...
US20140112074 INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES  
A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the...
US20130279256 Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits  
An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing...
US20130107628 Selective Word Line Erase In 3D Non-Volatile Memory  
An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or...
US20110116311 REDUCTION OF PUNCH-THROUGH DISTURB DURING PROGRAMMING OF A MEMORY DEVICE  
In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory...
US20110051517 PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES  
Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are...
US20100238729 NON-VOLATILE MEMORY WITH REDUCED LEAKAGE CURRENT FOR UNSELECTED BLOCKS AND METHOD FOR OPERATING SAME  
A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain...
US20090310414 NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same  
A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed...
US20090073763 METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on...
US20080049508 NONVOLATILE SEMICONDUCTOR MEMORY, ITS READ METHOD AND A MEMORY CARD  
A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection...
US20150262621 Non-Volatile Memory Which Can Increase the Operation Window  
A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of...
US20150103600 Nonvolatile Semiconductor Memory Device  
A non-volatile memory device, comprising: a substrate; a plurality of string stacks disposed over the substrate, each string stack comprising a long axis and a short axis in a plane parallel to...
US20140347935 METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE  
A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line...
US20140328128 NAND String Utilizing Floating Body Memory Cell  
NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string...
US20140241065 Vertically-Integrated Nonvolatile Memory Devices Having Laterally-Integrated Ground Select Transistors  
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This...
US20140092686 VERTICALLY-INTEGRATED NONVOLATILE MEMORY DEVICES HAVING LATERALLY-INTEGRATED GROUND SELECT TRANSISTORS  
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This...
US20140078826 Methods of Making Word Lines and Select Lines in NAND Flash Memory  
A NAND flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive...
US20130308385 APPARATUSES AND METHODS FOR COUPLING LOAD CURRENT TO A COMMON SOURCE  
Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage...
US20130286739 METHODS OF READING MEMORY CELLS  
Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to...
US20130250691 METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE  
A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line...
US20130201760 Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory  
A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel...
US20120120727 METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE  
A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line...
US20120075931 Techniques for the Fast Settling of Word Lines in NAND Flash Memory  
In non-volatile memory devices, a write operation typically consists of an alternating set of pulse and verify operations. After a pulse is applied, the device must be biased properly for an...