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US20090168513 MULTIPLE LEVEL CELL MEMORY DEVICE WITH IMPROVED RELIABILITY  
The reliability of multiple level cells in a memory device should be increased by programming the ends of the series strings of memory cells differently than the remaining quantity of memory cells...
US20120051139 REDUCING READ FAILURE IN A MEMORY DEVICE  
Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass...
US20110141810 READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR COUPLING  
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
US20110128782 REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE  
Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a...
US20100265771 METHOD OF PROGRAMMING MEMORY CELLS OF SERIES STRINGS OF MEMORY CELLS  
Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after programming each memory cell of the string...
US20140119122 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME  
A nonvolatile memory device and a method of programming the nonvolatile semiconductor memory device are disclosed. The programming method includes applying a first voltage greater than a ground...
US20130141977 Page Buffer Circuit  
A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A...
US20090273978 NAND FLASH MEMORY  
A NAND flash memory has a control circuit. The control circuit applies a writing voltage between a control gate and a well by applying a first voltage to the well and a positive second voltage...
US20140269076 NON-VOLATILE MEMORY AND PROGRAMMING IN THEREOF  
A non-volatile memory system includes a bit line and a plurality of memory cells associated with the bit line and coupled in a serial manner. The system further has a control circuitry in...
US20100074015 SENSING FOR MEMORY READ AND PROGRAM VERIFY OPERATIONS IN A NON-VOLATILE MEMORY DEVICE  
Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to...
US20100027341 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM  
A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a...
US20080181009 SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD THEREOF  
A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit...
US20150206587 METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY  
Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate...
US20090168526 FLASH MEMORY DEVICE HAVING DUMMY CELL  
A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string...
US20090109761 Method of operating nonvolatile memory device  
Provided is a method of operating a three-dimensional nonvolatile memory device which may increase the reliability and efficiency of the three-dimensional nonvolatile memory device. The method of...
US20090034336 Flash memory device having improved bit-line layout and layout method for the flash memory device  
Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double...
US20130308386 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor...
US20130088921 OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY  
An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a...
US20090296476 Flash Memory Device and Method for Manufacturing the Same  
A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe,...
US20090180324 Semiconductor Constructions, NAND Unit Cells, Methods Of Forming Semiconductor Constructions, And Methods Of Forming NAND Unit Cells  
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be...
US20140192594 P-CHANNEL 3D MEMORY ARRAY  
A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective...
US20090180325 Partitioned Erase And Erase Verification In Non-Volatile Memory  
A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase...
US20080239822 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME  
A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first...
US20150179275 ASYMMETRIC STATE DETECTION FOR NON-VOLATILE STORAGE  
Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines,...
US20130250687 SHARED-BIT-LINE BIT LINE SETUP SCHEME  
Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings,...
US20120170370 NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME  
A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell,...
US20110075484 NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME  
A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell,...
US20100097862 FLASH MEMORY DEVICES WITH MEMORY CELLS STRINGS INCLUDING DUMMY TRANSISTORS WITH SELECTIVE THRESHOLD VOLTAGES  
Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the...
US20100046294 NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME  
A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell...
US20090190405 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write...
US20070242514 NAND-structured nonvolatile memory cell  
A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain...
US20140269082 OPERATION FOR NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES  
A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate...
US20140112075 Pre-Charge During Programming For 3D Memory Using Gate-Induced Drain Leakage  
In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of...
US20140063960 MEMORY PROGRAM DISTURB REDUCTION  
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias...
US20130279258 PROGRAM CONDITION DEPENDENT BIT LINE CHARGE RATE  
Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may...
US20130128669 OPERATION FOR NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES  
A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate...
US20110134697 DYNAMIC PASS VOLTAGE FOR SENSE OPERATION IN A MEMORY DEVICE  
Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for...
US20090296477 Nonvolatile Memory Devices Having Electromagnetically Shielding Source Plates  
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors...
US20080031046 Nonvolatile Memory Array Having Modified Channel Region Interface  
The technology relates to nonvolatile memory with a modified channel region such as a raised source and drain or a recessed channel region.
US20140269079 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write...
US20130182505 FLASH PROGRAMMING TECHNOLOGY FOR IMPROVED MARGIN AND INHIBITING DISTURBANCE  
A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a...
US20090238003 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word...
US20090168532 NONVOLATILE MEMORY DEVICES THAT UTILIZE DUMMY MEMORY CELLS TO IMPROVE DATA RELIABILITY IN CHARGE TRAP MEMORY ARRAYS  
A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge...
US20060018159 Programmable NAND memory  
An electrically programmable memory including: an array of a plurality of memory cells arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks and...
US20140247662 Efficient Smart Verify Method For Programming 3D Non-Volatile Memory  
In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line...
US20140226406 Efficient Smart Verify Method For Programming 3D Non-Volatile Memory  
In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line...
US20120327715 NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN  
Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical...
US20110122691 POWER MANAGEMENT OF MEMORY SYSTEMS  
A memory system that includes a memory array and a memory controller manages power consumption by maintaining a variable credit value that reflects the amount of power available to the memory...
US20110096601 Non-Volatile Memory And Method With Accelerated Post-Write Read To Manage Errors  
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of...
US20100085812 Nonvolatile Memory Devices Having Common Bit Line Structure  
Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of...