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US20140369129 Method And Apparatus For Program And Erase Of Select Gate Transistors  
Techniques are provided for programming select gate transistors in connection with the programming of a set of memory cells. In response to a program command to program memory cells, the select...
US20100074017 Method for Programming Nand Type Flash Memory  
Disclosed is a method for programming a flash memory device capable of preventing a threshold voltage distribution of a memory cell from being moved due to a pass disturbance of the memory cell...
US20140269080 NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME  
A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with...
US20140192598 SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a...
US20130322178 SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a...
US20090279360 NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array  
A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR...
US20090168533 THREE-DIMENSIONAL MEMORY DEVICE AND PROGRAMMING METHOD  
A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each...
US20140362646 READING SOFT BITS SIMULTANEOUSLY  
Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling...
US20090187798 NONVOLATILE MEMORY HAVING NON-POWER OF TWO MEMORY CAPACITY  
A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the...
US20090190404 NAND FLASH CONTENT ADDRESSABLE MEMORY  
NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture...
US20100195398 APPLYING DIFFERENT BODY BIAS TO DIFFERENT SUBSTRATE PORTIONS FOR NON-VOLATILE STORAGE  
Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code...
US20090016111 Flash memory device and program recovery method thereof  
A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to...
US20090168523 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address...
US20120218822 CONTENT ADDRESSABLE MEMORY  
NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture...
US20100002503 Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation  
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a...
US20090103364 SERIAL INTERFACE NAND  
Embodiments are provided that include operating a NAND memory device via an SPI interface. One such method includes cache loading a NAND memory device including loading data into a cache of the...
US20130294167 Erase Inhibit For 3D Non-Volatile Memory  
An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the...
US20130163337 Erase Inhibit For 3D Non-Volatile Memory  
An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the...
US20080205147 Local self-boost inhibit scheme with shielded word line  
A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent...
US20070070699 Nonvolatile semiconductor memory device having dummy bit line with multiple sections  
A nonvolatile semiconductor memory device is disclosed having a dummy bit line formed from a plurality of dummy bit line sections. The particular dummy bit line sections are variously connected a...
US20140160850 STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME  
Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and...
US20120182805 STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME  
Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and...
US20140355352 MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE  
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory...
US20140063959 MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE  
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory...
US20110194348 DYNAMIC AND ADAPTIVE OPTIMIZATION OF READ COMPARE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION  
A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One...
US20100259987 Two Pass Erase For Non-Volatile Storage  
Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the...
US20080232170 MEMORY DEVICE, A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE  
A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a...
US20130314995 Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory  
A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively...
US20080186765 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device according to one example includes a first cell transistor series including memory cell transistor connected in series, a first selecting transistor whose one terminal...
US20110007568 NAND TYPE ROM  
The invention discloses a NAND type ROM. The NAND type ROM comprises a plurality of bit lines, a plurality of word lines, a first source line, a second source line, and a plurality of NAND...
US20090016110 METHODS OF READING DATA FROM NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically...
US20090310415 NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND STRINGS AND METHODS OF FORMING THE SAME  
A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective...
US20120236647 HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY  
Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic...
US20110235424 HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY  
Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic...
US20110149655 Non-volatile memory cell array  
A non-volatile microelectronic memory that has a memory cell array, which includes memory cell string pairs that share a bitline contact, that have separate source lines, and that have at least...
US20090251962 Three-Dimensional Memory Device and Driving Method Thereof  
A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A...
US20090097318 Programming sequence in NAND memory  
An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source follower sensing by programming the...
US20130188423 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME  
According to example embodiments of inventive concepts, a nonvolatile memory device includes a first NAND string and a second NAND string. The first NAND string include a first string selection...
US20140269077 ARRAY ARRANGEMENT FOR 3D NAND MEMORY  
A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The...
US20090307414 MEMORY SYSTEM, MEMORY SYSTEM CONTROL METHOD, AND DRIVE RECORDER APPARATUS  
A memory system includes a NAND-type flash memory which includes a plurality of memory cells and can store one-bit, two-bit or more data in one memory cell, and a duplicating-converting circuit...
US20130258780 METHOD OF PROGRAMMING SELECTION TRANSISTORS FOR NAND FLASH MEMORY  
Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to...
US20080273390 NAND flash memory cell array and method of fabricating the same  
A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality...
US20080089129 Flash memory device with flexible address mapping scheme  
A flash memory device includes a flash memory cell array which includes a plurality of memory cells arranged in rows and columns, reading and programming circuitry configured to read data from and...
US20090067246 Methods to Prevent Program Disturb in Nonvolatile Memory  
Methods are provided to be used individually or in any combination that reduce program disturb in a non-volatile memory consisting of dual-gate memory cells. These methods counteract the effect of...
US20100277983 Two Pass Erase For Non-Volatile Storage  
Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the...
US20150078089 METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS AND SELECT GATES WITH DOUBLE GATES  
An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate....
US20120275227 PHOTOSENSITIVE COMPOSITION AND COMPOUND FOR USE IN THE PHOTOSENESITIVE COMPOSITION  
A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and...
US20120147676 NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE  
A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate...
US20090122613 Non-volatile memory device and method of operating the same  
A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection...
US20140269083 BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS  
Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in...