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US20110235420 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE  
Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling...
US20100329010 READ OPERATION FOR MEMORY WITH COMPENSATION FOR COUPLING BASED ON WRITE-ERASE CYCLES  
A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold...
US20090279359 NAND WITH BACK BIASED OPERATION  
Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such...
US20080266924 NAND INTERFACE  
A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin.
US20090103362 SYSTEM AND METHOD FOR SETTING ACCESS AND MODIFICATION FOR SYNCHRONOUS SERIAL INTERFACE NAND  
The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device....
US20140293699 High Endurance Nonvolatile Memory  
A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase...
US20050157563 Memory Device and mobile communication device using a specific access procedure  
A memory device for a mobile communication device. The device includes a pseudo static random access memory (PSRAM), a NAND flash memory, an interface controller and a NOR flash memory. When the...
US20150085575 Multi-Word Line Erratic Programming Detection  
Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first...
US20060227611 Recovery method of NAND flash memory device  
A NAND flash memory device is recovered by applying a predetermined bias to a drain or a source. A negative bias is applied to a cell gate so that electrons are injected into a floating gate of a...
US20150078090 3D Non-Volatile Storage With Transistor Decoding Structure  
Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area...
US20130272069 3D NON-VOLATILE STORAGE WITH TRANSISTOR DECODING STRUCTURE  
Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area...
US20140247665 Select Transistor Tuning  
In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates...
US20140169095 Select Transistor Tuning  
In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates...
US20080239820 SELF-ADAPTIVE AND SELF-CALIBRATED MULTIPLE-LEVEL NON-VOLATILE MEMORIES  
Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed...
US20100074014 DATA STATE-BASED TEMPERATURE COMPENSATION DURING SENSING IN NON-VOLATILE MEMORY  
Temperature effects in a non-volatile storage device are addressed by providing a data state-dependent, and optionally temperature dependent, sense current during verify and read operations. A...
US20070223279 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
A semiconductor integrated circuit device 1 includes a plurality of basic cells 5 each having therein a logic transistor 2 that performs logical operations, and a power switching transistor 3 that...
US20110026327 BIT-LINE CONNECTIONS FOR NON-VOLATILE STORAGE  
Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and...
US20140126291 3D STACKED NON-VOLATILE STORAGE PROGRAMMING TO CONDUCTIVE STATE  
Programming NAND strings in a 3D stacked storage device to a conductive state is disclosed. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may...
US20090113166 HASHING METHOD FOR NAND FLASH MEMORY  
In accordance with exemplary embodiments, a flash memory, such as a NAND flash memory, selectively updates blocks based on hash values associated with the blocks, wherein the hashing codes are...
US20090225599 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE  
A nonvolatile semiconductor memory comprising: a plurality of memory cell blocks each including a plurality of memory cells serially connected to each other; a word line that is connected to...
US20090190398 Method of programming data in a NAND flash memory device and method of reading data in the NAND flash memory device  
A method of programming data in a NAND flash memory device including at least one even bitline and at least one odd bitline, the method including programming N-bit data into first cells coupled to...
US20090296473 Method of Forming an Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers and Corresponding Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers  
The present invention provides an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines. Further, the present...
US20070230249 Verification method for nonvolatile semiconductor memory device  
The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory...
US20140293702 Select Gate Materials Having Different Work Functions In Non-Volatile Memory  
In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different work functions in their...
US20090161437 HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY  
Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic...
US20140108891 MANAGING NON-VOLATILE MEDIA  
Apparatuses, systems, and methods are disclosed to manage non-volatile media. A method includes determining a configuration parameter for a set of storage cells of a non-volatile recording medium....
US20140003150 SYSTEM TO REDUCE STRESS ON WORD LINE SELECT TRANSISTOR DURING ERASE OPERATION  
A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the...
US20120081963 MULTI-STEP CHANNEL BOOSTING TO REDUCE CHANNEL TO FLOATING GATE COUPLING IN MEMORY  
In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce...
US20090129146 MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE  
In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to...
US20100246257 FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION  
Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have...
US20080080246 Flash memory device which includes strapping line connected to selection line  
A NAND flash array includes a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, memory cells operably coupled to word...
US20080273389 Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings  
Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate...
US20120117307 NON-VOLATILE MEMORY (NVM) ERASE OPERATION WITH BROWNOUT RECOVERY TECHNIQUE  
A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly...
US20120275226 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING POWER CONSUMPTION  
According to one embodiment, a nonvolatile semiconductor memory device includes an electrically rewritable nonvolatile memory, a grounding pad, a first power supply pad, a second power supply pad,...
US20090242958 NAND-TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor...
US20130215679 NONVOLATILE MEMORY DEVICE AND A METHOD OF ADJUSTING A THRESHOLD VOLTAGE OF A GROUND SELECTION TRANSISTOR THEREOF  
A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a...
US20070133289 NAND-type flash memory device with high voltage PMOS and embedded poly and methods of fabricating the same  
The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present...
US20050265076 Method of forming a vertical NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory...
US20110019478 SENSING OF MEMORY CELLS IN NAND FLASH  
An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage...
US20150200014 Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory  
A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively...
US20120300550 Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation  
In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more...
US20150009759 SUBSTRATE CONNECTION OF THREE DIMENSIONAL NAND FOR IMPROVING ERASE PERFORMANCE  
A memory includes a doped substrate well, a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well. A series...
US20080013377 Non-volatile memory devices including dummy word lines and related structures and methods  
A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string...
US20060203552 Process of Fabricating Flash Memory with Enhanced Program and Erase Coupling  
Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source...
US20110199827 MEMORY ARRAY HAVING MEMORY CELLS COUPLED BETWEEN A PROGRAMMABLE DRAIN SELECT GATE AND A NON-PROGRAMMABLE SOURCE SELECT GATE  
Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of...
US20090207657 MULTI LEVEL INHIBIT SCHEME  
Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels...
US20140254277 Method And Apparatus For Program And Erase Of Select Gate Transistors  
Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program...
US20140198575 Method And Apparatus For Program And Erase Of Select Gate Transistors  
Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program...
US20090046515 NOR Flash Memory Device and Method for Fabricating the Same  
Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns....
US20090287879 NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME  
An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC....