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US20090251968 Integrated circuit having a base structure and a nanostructure  
In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically...
US20150179267 PROGRAM VT SPREAD FOLDING FOR NAND FLASH MEMORY PROGRAMMING  
Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular,...
US20140247663 NON-VOLATILE STORAGE WITH PROCESS THAT REDUCES READ DISTURB ON END WORDLINES  
A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have...
US20150003161 System for Maintaining Back Gate Threshold Voltage in Three Dimensional NAND Memory  
In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage...
US20090238001 Interface for NAND-Type Flash Memory  
A NAND-type flash memory device is described. In some embodiments, the memory device includes NAND-type flash memory cells, and a synchronous NAND interface. The synchronous NAND interface...
US20120307561 NON-VOLATILE MEMORY DEVICE AND METHOD CONTROLLING DUMMY WORD LINE VOLTAGE ACCORDING TO LOCATION OF SELECTED WORD LINE  
A non-volatile memory device includes access circuitry that selects a word line during an operation, applies a selected word line voltage to the selected word line, applies a non-selected word...
US20100074020 CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE  
A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load...
US20130322174 Threshold Voltage Adjustment For A Select Gate Transistor In A Stacked Non-Volatile Memory Device  
In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To...
US20120327713 IN-FIELD BLOCK RETIRING  
Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad...
US20140153334 TERMINATION FOR COMPLEMENTARY SIGNALS  
Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including...
US20150003162 Detecting Programmed Word Lines Based On NAND String Current  
A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive...
US20120087190 Write BIAS condition for 2T-string NOR flash cell  
This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias...
US20130114342 DEFECTIVE WORD LINE DETECTION  
Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements...
US20070147120 Page buffer and related reading method  
A page buffer and a reading method comprising a unitary operation adapted to execute either a normal read operation or a copyback read operation using a page buffer are disclosed. The unitary...
US20100322006 NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME  
A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate...
US20120250414 REDUCING NEIGHBOR READ DISTURB  
Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to...
US20130294169 SIMULTANEOUS MULTI-LEVEL BINARY SEARCH IN NON-VOLATILE STORAGE  
Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling...
US20070247910 NAND erase block size trimming apparatus and method  
A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure, the string subdivided by a plurality of separator elements placed in series with the memory cells...
US20110075480 Non-Volatile Memory With Improved Sensing By Reducing Source Line Current  
One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and...
US20130163330 MITIGATING VARIATIONS ARISING FROM SIMULTANEOUS MULTI-STATE SENSING  
Methods and devices for mitigating sensing variations that may arise from simultaneous multi-threshold (SMT) sensing are provided. During SMT sensing, two or more different bias conditions may be...
US20110188312 METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS  
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory...
US20140219027 Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level  
Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming...
US20140192597 CIRCUIT FOR CONTROLLING EEPROM CELL  
An EEPROM cell control circuit is provided which includes a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control...
US20130070531 SUBSTRATE BIAS DURING PROGRAM OF NON-VOLATILE STORAGE  
A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the...
US20090196102 FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES  
A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory...
US20080181008 FLASH MEMORY SYSTEM CAPABLE OF IMPROVING ACCESS PERFORMANCE AND ACCESS METHOD THEREOF  
A flash memory system capable of improving an access performance and an access method thereof. The system includes: a flash memory device including a plurality of storage regions; a contents...
US20090097317 Integrated Circuit Having NAND Memory Cell Strings  
Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a...
US20100097861 Multi-Pass Programming For Memory Using Word Line Coupling  
A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different...
US20090175081 NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES  
A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors....
US20150170748 Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current  
An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in...
US20130279257 Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current  
An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in...
US20100157678 NON-VOLATILE MEMORY WITH BOOST STRUCTURES  
A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading...
US20120300551 NON-VOLATILE MEMORY CELL HEALING  
Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a...
US20070183204 NAND-type nonvolatile memory devices having common bit lines and methods of operating the same  
A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line,...
US20090180330 NON-VOLATILE MEMORY DEVICE AND METHODS OF USING  
The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.
US20120147675 Nonvolatile Stacked Nand Memory  
A NAND string of memory cells has stacks of split word lines (gates), with resulting increased bit density. Variants add a top assist gate to the NAND string, a bottom assist gate to the NAND...
US20110194351 SOURCE SIDE ASYMMETRICAL PRECHARGE PROGRAMMING SCHEME  
A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a...
US20090323421 MEMORY DEVICE WITH POWER NOISE MINIMIZATION DURING SENSING  
Accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed...
US20100085811 SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME  
A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that...
US20140022841 Memory System with Unverified Program Step  
In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps....
US20080031052 A DOUBLE-BIAS ERASE METHOD FOR MEMORY DEVICES  
A dual-bias erase process for a non-volatile memory device is described. The dual-bias erase process applies a positive bias to the source and drain regions of the memory device, while...
US20120155177 STRUCTURES AND METHODS FOR READING OUT NON-VOLATILE MEMORY USING REFERENCING CELLS  
The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the...
US20100027340 PATTERN DEPENDENT STRING RESISTANCE COMPENSATION  
Pattern dependent string resistance compensation of a memory device is generally described. In one example, an electronic device includes a first string of memory cells and a first bit line...
US20100002516 Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same  
Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string....
US20080253181 METHOD FOR PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE  
A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are...
US20080170440 FLASH MEMORY DEVICE WITH SPLIT STRING SELECTION LINE STRUCTURE  
A flash memory device is disclosed and includes a memory cell array including a plurality of sectors. Each one of the plurality of sectors includes a plurality of strings, and each of the...
US20120176838 REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE  
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word...
US20140185384 NONVOLATILE MEMORY DEVICES INCLUDING SIMULTANEOUS IMPEDANCE CALIBRATION  
An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration...
US20090323420 MINIMIZING POWER NOISE DURING SENSING IN MEMORY DEVICE  
In a sensing method, accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different...
US20120250415 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE  
Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling...