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US20130242660 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, in a write control unit that performs writing on a selected memory cell connected to a selected word line by making to apply a program voltage to the selected word...
US20130235668 SEMICONDUCTOR DEVICE  
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage,...
US20130235666 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACURING THE SAME  
A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality...
US20130229873 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat...
US20130201762 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a control circuit of a memory cell array is configured to write data to a memory cell array by applying a first write pass voltage, which is lower than the program...
US20130201761 SENSE AMPLIFIER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a...
US20130194872 NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF  
Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the...
US20130194871 NAND FLASH MEMORY UNIT, NAND FLASH MEMORY ARRAY, AND METHODS FOR OPERATING THEM  
A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a...
US20130194870 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME  
A semiconductor memory device includes a memory block including memory strings coupled to and disposed between bit lines and a common source line, and a peripheral circuit configured to perform a...
US20130170300 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate...
US20130163338 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE  
Provided is a non-volatile semiconductor storage device including: a memory cell array where memory cells are arranged in a matrix shape; and a control unit which erases the memory cell by...
US20130121079 NOR FLAH MEMORY CELL AND STRUCTURE THEREOF  
The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a...
US20130114341 Method and Apparatus for Indicating Bad Memory Areas  
Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory...
US20130107629 NONVOLATILE MEMORY DEVICES AND OPERATING METHODS THEREOF  
According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least...
US20130094294 NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE  
Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory cells to judge an erase state and at...
US20130088918 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A non-volatile semiconductor memory device includes a semiconductor layer of a first conductivity type, and a plurality of wells of a second conductivity type formed on the first semiconductor...
US20130083603 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
One embodiment includes a write control unit that performs a first write operation with respect to a first threshold distribution, a first verify operation on the first threshold distribution, and...
US20130083602 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a write control unit performs a condition verify operation of searching for a low level region and a high level region of memory cells, and sets a write voltage of the...
US20130077404 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read...
US20130051147 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device includes bit lines, word lines, NAND strings, source lines, first and second select gate transistors, and a controller. After giving a first potential to...
US20130044544 NONVOLATILE MEMORY DEVICE  
According to one embodiment, a nonvolatile memory device includes a circuit and a memory cell. The circuit outputs a program voltage. The memory cell is programmed data by being applied the...
US20130021848 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE THEREIN  
A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The...
US20130021847 NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD  
A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic...
US20130007349 SMART BRIDGE FOR MEMORY CORE  
An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the...
US20130003461 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE  
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The...
US20130003458 NAND ARCHITECTURE MEMORY WITH VOLTAGE SENSING  
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor...
US20120327714 Memory Architecture of 3D Array With Diode in Memory String  
Various embodiments are directed to 3D memory arrays that lack a select line and devices controlled by the select line between one of the source line and the bit line, and the memory cells. Diodes...
US20120287716 Using Channel-To-Channel Coupling To Compensate Floating Gate-To-Floating Gate Coupling In Programming Of Non-Volatile Memory  
In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used...
US20120281475 NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME  
An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC....
US20120243317 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a non-volatile semiconductor memory device includes a writing unit that performs a writing operation on memory cells while stepping up a writing voltage based on a...
US20120213006 SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE  
A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective...
US20120206968 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution...
US20120195123 Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory  
A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their...
US20120182806 Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures  
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled...
US20120182804 ARCHITECTURE FOR A 3D MEMORY ARRAY  
Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also...
US20120182802 Memory Architecture of 3D Array With Improved Uniformity of Bit Line Capacitances  
A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in...
US20120163083 ALTERNATE BIT LINE BIAS DURING PROGRAMMING TO REDUCE CHANNEL TO FLOATING GATE COUPLING IN MEMORY  
In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse....
US20120155180 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE  
A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a...
US20120155179 SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to...
US20120155178 SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a semiconductor memory device includes a memory, and a data transfer section configured to perform data transfer from and to the memory, and having a first mode to...
US20120134212 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory...
US20120127797 SYSTEM AND METHOD FOR TESTING FOR DEFECTS IN A SEMICONDUCTOR MEMORY ARRAY  
A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level...
US20120092931 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set...
US20120081965 METHOD OF EVALUATING A SEMICONDUCTOR STORAGE DEVICE  
A method of evaluating a semiconductor storage device of a floating gate type has calculating an electron density distribution of a tunnel insulating film of a memory cell by multiplying a change...
US20120069667 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SPEEDING UP DATA WRITE  
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array having a plurality of memory cells is connected to...
US20120051138 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME  
A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a...
US20120051137 Memory Architecture of 3D Array With Diode In Memory String  
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled...
US20120051136 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME  
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a string selection line (SSL), the memory cells associated with the SSL...
US20120044765 WORD LINE ACTIVATION IN MEMORY DEVICES  
Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an...
US20120008399 METHODS OF OPERATING MEMORIES INCLUDING CHARACTERIZING MEMORY CELL SIGNAL LINES  
Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states...