Match Document Document Title
US20140160849 METHOD AND APPARATUS FOR INDICATING BAD MEMORY AREAS  
Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory...
US20140146609 Weighted Read Scrub For Nonvolatile Memory  
In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially...
US20140140137 NAND-TYPE NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE  
According to one embodiment, a NAND-type non-volatile semiconductor storage includes a memory cell array and a control circuit. The memory cell array has a memory string in which more than one of...
US20140136760 DE-DUPLICATION SYSTEM USING NAND FLASH BASED CONTENT ADDRESSABLE MEMORY  
A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so...
US20140133239 MEMORY DEVICES HAVING SELECT GATES WITH P TYPE BODIES, MEMORY STRINGS HAVING SEPARATE SOURCE LINES AND METHODS  
Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type...
US20140133237 On-Device Data Analytics Using NAND Flash Based Intelligent Memory  
A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so...
US20140104951 SENSING DATA STORED IN MEMORY  
The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and...
US20140098612 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor...
US20140092685 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME  
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells...
US20140085983 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF  
A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected...
US20140085982 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which...
US20140085979 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A memory cell array according to an embodiment includes a plurality of NAND strings with a plurality of memory cells stacked, and a bit line is connected to the NAND string. A word line is...
US20140082345 SEMICONDUCTOR DEVICE  
On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m...
US20140078827 APPARATUSES AND METHODS INCLUDING MEMORY ARRAY AND DATA LINE ARCHITECTURE  
Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a...
US20140071760 SYSTEMS AND METHODS FOR ERASING CHARGE-TRAP FLASH MEMORY  
FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory...
US20140071759 NONVOLATILE MEMORY DEVICE  
According to an embodiment, a nonvolatile memory device includes a plurality of memory cell strings disposed in parallel in a first direction, a bit line and a first contact plug. Each of the...
US20140063965 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate...
US20140063964 SEMICONDUCTOR MEMORY DEVICE  
According to an embodiment, sense amplifiers are arranged one by one within an arrangement width of k bit lines in a direction of the bit lines, and determine data stored in the memory cells,...
US20140063963 SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a semiconductor memory device includes a memory core including a memory cell array, and a peripheral circuit configured to transfer data input to a pad unit to the...
US20140063962 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a memory cell array in which memory cells are arranged, and a first wiring connected to the memory cells. A discharging circuit discharges the voltage of the...
US20140063951 SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME  
An operating method of a semiconductor memory device is provided. The method includes supplying a first voltage to a selected bit line where a selected memory cell among memory cells is connected...
US20140063940 ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE  
Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be...
US20140050027 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution...
US20140050023 MEMORY DEVICE HAVING COLLABORATIVE FILTERING TO REDUCE NOISE  
An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative...
US20140043909 WRITING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, there is provided a writing method. The method includes setting potentials of a plurality of word lines to a first potential. The first potential is a potential to...
US20140036592 SEMICONDUCTOR STORAGE DEVICE  
A semiconductor storage device has a memory cell array including memory cells and a plurality of redundancy regions arranged in a first direction including flag cells, plural word lines extending...
US20140029344 NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME  
Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular...
US20140029343 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors configured to store information in accordance with n (n is an...
US20140003151 SELECT GATE PROGRAMMING IN A MEMORY DEVICE  
Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit...
US20140003149 SEMICONDUCTOR STORAGE DEVICE  
According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and...
US20140003148 THREE DIMENSIONAL NAND FLASH WITH SELF-ALIGNED SELECT GATE  
An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory...
US20130343130 NAND FLASH BIASING OPERATION  
A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a...
US20130336065 ARCHITECTURE FOR 3-D NAND MEMORY  
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components,...
US20130329500 NONVOLATILE MEMORY DEVICE, ERASING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME  
Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies...
US20130329499 MEMORY CELL STRING BASED ON GATED-DIODE CELL AND MEMORY ARRAY USING THE SAME  
The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a...
US20130322179 HOT CARRIER PROGRAMMING IN NAND FLASH  
A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by...
US20130322177 INTEGRATED CIRCUIT AND APPARATUSES INCLUDING THE SAME  
An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit...
US20130314997 Memory Access Method and Flash Memory Using the Same  
A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory...
US20130314996 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE  
According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a...
US20130294168 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the...
US20130294166 NON-VOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME  
A non-volatile memory device and a method for driving the same are disclosed. During a precharge operation, the bit line is precharged on the basis of a voltage applied to a common source line....
US20130294165 SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND CONTROL METHOD THEREOF  
A semiconductor memory device includes first cell strings connected to first bit lines and second cell strings connected to second bit lines corresponding to the first bit lines, respectively....
US20130286738 SEMICONDUCTOR MEMORY APPARATUS  
According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes...
US20130279255 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME  
According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a...
US20130265826 MEMORY SYSTEM AND OPERATING METHOD OF CONTROLLER  
A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second...
US20130258782 CONFIGURATION MEMORY  
According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are...
US20130258781 MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES  
Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a...
US20130258776 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA THEREFROM  
A non-volatile semiconductor memory device according to an aspect includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory cells, and stores initial...
US20130242662 METHOD FOR DRIVING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface...
US20130242661 NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB  
A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read...