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US20160086665 MEMORY ARCHITECTURE OF THIN FILM 3D ARRAY  
A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the...
US20160078953 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a first memory cell and a second memory cell having a parasitic capacitance smaller than a parasitic capacitance of the first memory cell, a first bit line...
US20160078948 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a first memory string including a first memory cell and a second memory cell, a second memory string including a third memory cell, a bit line connected to...
US20160078941 SEMICONDUCTOR MEMORY DEVICE INCLUDING A NAND STRING  
A semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select...
US20160071876 MULTI-CHARGE REGION MEMORY CELLS FOR A VERTICAL NAND DEVICE  
A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are...
US20160071595 Controlling Pass Voltages To Minimize Program Disturb In Charge-Trapping Memory  
Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer,...
US20160064090 Charge Redistribution During Erase In Charge Trapping Memory  
Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after...
US20160064088 SEMICONDUCTOR MEMORY DEVICE AND DATA ERASING METHOD  
A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the...
US20160064087 Charge Redistribution During Erase In Charge Trapping Memory  
Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after...
US20160055915 Avoiding Unintentional Program Or Erase Of A Select Gate Transistor  
Techniques are provided for preventing inadvertent program or erase of select gate transistors and dummy memory cells during an erase operation involving data-storing memory cells in a...
US20160055911 Techniques for Programming of Select Gates in NAND Memory  
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages,...
US20160049199 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME  
A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a...
US20160042771 TIMED MULTIPLEX SENSING  
Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time...
US20160035424 Systems and methods for trimming control transistors for 3D NAND flash  
Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process....
US20160027520 SEMICONDUCTOR MEMORY DEVICE INCLUDING THREE-DIMENSIONAL MEMORY CELL ARRAY STRUCTURE AND OPERATING METHOD THEREOF  
An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines;...
US20160027514 NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF  
According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory...
US20160027512 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME  
A nonvolatile semiconductor memory device according to an embodiment includes a control unit, during the read sequence performed to an interested cell, performing a first read operation to detect...
US20160019971 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME  
According to an embodiment, a non-volatile semiconductor memory device comprises a NAND cell unit, a bit-line, a source-line, word-lines and a control circuit. The NAND cell unit comprises memory...
US20160012898 MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF  
A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of...
US20160012897 NONVOLATILE MEMORY DEVICE, A STORAGE DEVICE HAVING THE SAME AND AN OPERATING METHOD OF THE SAME  
An operating method of a nonvolatile memory device including a plurality of strings each string including at least two pillars penetrating wordlines disposed at different layers. The operating...
US20160005491 Look Ahead Read Method For Non-Volatile Memory  
A read operation for selected memory cell on a selected word line compensates for program disturb which is a nonlinear function of the data state of an adjacent memory cell on an adjacent word...
US20160005480 NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME  
A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a...
US20160005479 READING METHOD FOR A CELL STRING  
A reading method for a cell string includes a pre-charging step and a reading step to read a selected word line cell WL[k]. The pre-charging step comprises applying a positive pass voltage...
US20160005474 MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF  
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a...
US20160005466 SEMICONDUCTOR DEVICE  
A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed on a pipe transistor of a...
US20150380422 Vertical Floating Gate NAND with Selectively Deposited ALD Metal Films  
A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of...
US20150380092 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash...
US20150371996 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME  
A memory device includes an array of floating gate memory cells. Adjacent memory cells are separated by a plurality of air gaps that electrically decouple respective active regions of adjacent...
US20150371709 Three Dimensional Vertical NAND Device With Floating Gates  
A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a...
US20150340369 3D INDEPENDENT DOUBLE GATE FLASH MEMORY  
A memory device configurable for independent double gate cells, storing multiple bits per cell includes multilayer stacks of conductive strips configured as word lines. Active pillars are disposed...
US20150325304 METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE  
A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line...
US20150294729 COMPENSATING FOR OFF-CURRENT IN A MEMORY  
A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current...
US20150294727 SENSING MEMORY CELLS COUPLED TO DIFFERENT ACCESS LINES IN DIFFERENT BLOCKS OF MEMORY CELLS  
In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently...
US20150294726 NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME  
A NAND-type flash memory device and method for programming the NAND-type flash memory device are provided. The method may include applying a voltage of 0 V to an unselected string select line,...
US20150262699 SEMICONDUCTOR MEMORY DEVICE AND MEMORY CONTROLLER  
A semiconductor memory device includes a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase...
US20150262698 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a block including a plurality of string units, each including a plurality of memory cells electrically connected in series, a bad string register in which...
US20150262688 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device according to one embodiment includes a control circuit. The control circuit is configured to apply, when reading data of a first selected memory cell...
US20150243358 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate...
US20150228350 CURRENT DETECTION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS  
The invention provides a current detection circuit and a semiconductor memory apparatus using the current detection circuit thereof. The current detection circuit is capable of rapidly sensing the...
US20150228347 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF  
A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection...
US20150221389 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF  
Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain...
US20150221387 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME  
According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory...
US20150221381 MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AN ERASE METHOD THEREOF  
An erase method of a three-dimensional nonvolatile memory device may include receiving an erase command, applying an erase voltage to perform an erase operation to a selected memory region in...
US20150213903 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading...
US20150187422 SEMICONDUCTOR DEVICE  
A semiconductor device includes first memory strings coupled between a first common source line formed on a substrate and bit lines formed over the first common source line, and second memory...
US20150179273 MEMORY READ APPARATUS AND METHODS  
Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated...
US20150162084 ARCHITECTURE FOR 3-D NAND MEMORY  
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components,...
US20150131381 Three Dimensional Nonvolatile Memory Cell Structure with Upper Body Connection  
A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection...
US20150124530 MEMORY STRING AND SEMICONDUCTOR DEVICE INCLUDING THE SAME  
A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source...
US20150124528 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which...