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US20130128666 Scrub Techniques for Use with Dynamic Read  
The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured...
US20150085574 Back Gate Operation with Elevated Threshold Voltage  
In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor...
US20090201734 Verified purge for flash storage device  
A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller...
US20090046513 Enhanced erase for flash storage device  
A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used subsequent to the erase. A flash...
US20130336059 BLOCK LEVEL GRADING FOR RELIABILITY AND YIELD IMPROVEMENT  
A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of...
US20120002473 BACKGROUND POWER CONSUMPTION REDUCTION OF ELECTRONIC DEVICES  
An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding...
US20130070530 HIGH ENDURANCE NON-VOLATILE STORAGE  
A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
US20080008001 Semiconductor device and boot method for the same  
A semiconductor device is designed to provide an access control for a memory that includes a plurality of storage regions storing the same boot programs comprised of a set of program data. The...
US20090201732 System and method for purging a flash storage device  
A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and...
US20140098610 Erased State Reading  
Memory cells that are indicated as being erased but are suspected of being partially programmed may be subject to a verification scheme that first performs a conventional read and then, if the...
US20130258779 NAND MEMORY ARRAY WITH MISMATCHED CELL AND BITLINE PITCH  
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mis-matched cell and bitline pitch. Other embodiments may be described and...
US20080101120 METHOD OF PROGRAMMING MULTI-PAGES AND FLASH MEMORY DEVICE OF PERFORMING THE SAME  
In programming multi-pages in a flash memory device, a first page group and a second page group are formed with respect to each of at least one memory plane by grouping page buffers such that...
US20140247660 Compensation for Sub-Block Erase  
A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could...
US20140133232 Compensation for Sub-Block Erase  
A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could...
US20090323417 SEMICONDUCTOR MEMORY REPAIRING A DEFECTIVE BIT AND SEMICONDUCTOR MEMORY SYSTEM  
A semiconductor memory has a plurality of blocks, and each of the blocks comprises a plurality of pages, and further, each of the pages has a plurality of memory cells. A block having defective...
US20130107627 BACK-BIASING WORD LINE SWITCH TRANSISTORS  
Back biasing word line switch transistors is disclosed. One embodiment includes word line switch transistors that are in a well in a substrate. A memory array having non-volatile storage devices...
US20090310411 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS  
An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing...
US20120314495 APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB  
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as...
US20070211531 INTEGRATED CIRCUIT HAVING A WORD LINE DRIVER  
An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver...
US20090154245 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE  
A nonvolatile semiconductor storage device includes: a memory cell array in which electrically rewritable nonvolatile memory cells are arranged; and a register that holds good/bad information on a...
US20120314499 INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE  
A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current...
US20090109756 MEMORY DEVICE WITH VARIABLE TRIM SETTING  
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim...
US20050213380 Multiple power source-semiconductor integrated circuit  
In a multiple power source semiconductor integrated circuit that is manufactured using a process which generates a large leakage current, supply of power to a function block that is not being used...
US20090034333 Method for Managing a Non-Volatile Memory In a Smart Card  
The invention concerns a method for managing access to a non-volatile memory (VNVM), characterized in that said non-volatile memory (VNVM) results from the association of a non-volatile memory of...
US20140003147 Optimized Erase Operation For Non-Volatile Memory With Partially Programmed Block  
In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial...
US20140126286 SINGLE-LEVEL CELL ENDURANCE IMPROVEMENT WITH PRE-DEFINED BLOCKS  
Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel...
US20140347928 LOW DISTURBANCE, POWER-CONSUMPTION, AND LATENCY IN NAND READ AND PROGRAM-VERIFY OPERATIONS  
A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge...
US20150063028 Bad Block Reconfiguration in Nonvolatile Memory  
When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing...
US20080247233 NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE  
A nonvolatile memory device which can reduce consumption current and shorten access time and a control method thereof is provided. The nonvolatile memory device 1 comprises a booster controller...
US20090109755 Neighbor block refresh for non-volatile memory  
Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a...
US20150063026 CONTINUOUS ADJUSTING OF SENSING VOLTAGES  
The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an error rate associated with sense...
US20070081386 Methods, circuits and computer program products for updating data in non-volatile memories  
A method of updating data, which is stored in each page in a non-volatile memory with a multi-plane structure, using an external buffer, is provided. In the method, source data that will not be...
US20090323419 READ-TIME WEAR-LEVELING METHOD IN STORAGE SYSTEM USING FLASH MEMORY DEVICE  
Disclosed is a read-time wear-leveling method in a storage system using a flash memory device, in which the abrasion of the flash memory device generated by repeated read operations is dispersed...
US20100020614 Non-Volatile Memory With Linear Estimation of Initial Programming Voltage  
In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is...
US20090040827 Flash memory device for remapping bad blocks and bad block remapping method  
Provided are a flash memory device and a bad block remapping method thereof. The flash memory device includes: an address storage block detecting whether a block address provided from the outside...
US20150124527 Detecting Programmed Word Lines Based On NAND String Current  
A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive...
US20150138887 METHOD AND SYSTEM FOR IMPROVING THE RADIATION TOLERANCE OF FLOATING GATE MEMORIES  
A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A...
US20110249501 DYNAMIC POLARIZATION FOR REDUCING STRESS INDUCED LEAKAGE CURRENT  
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.
US20140376311 METHOD AND APPRATUS FOR SHORTENED ERASE OPTION  
A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
US20130070529 Semiconductor device and operating method thereof  
A method of operating a semiconductor device includes programming one of a drain dummy cell and a source dummy cell which are included in a cell string; and coupling a bit line to the cell string...
US20140010013 MEMORY ERASING METHOD AND DRIVING CIRCUIT THEREOF  
A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are...
US20140233315 3D STACKED NAND FLASH MEMORY ARRAY HAVING SSL STATUS CHECK BUILDINGS FOR MONITORING THRESHOLD VOLTAGES OF STRING SELECTION TRANSISTORS AND METHODS FOR MONITORING AND OPERATING THE SAME  
Disclosed is a 3D stacked NAND flash memory array having SSL status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of...
US20070247910 NAND erase block size trimming apparatus and method  
A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure, the string subdivided by a plurality of separator elements placed in series with the memory cells...
US20110267885 NON-VOLATILE MEMORY AND METHOD WITH EVEN/ODD COMBINED BLOCK DECODING  
A nonvolatile memory array is organized into a plurality of interleaving even and odd blocks. When a block is selected for operation, a set of word line voltages are delivered to the block of word...
US20130343127 METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS  
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory...
US20120327712 METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS  
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory...
US20130272067 NON-BOOSTING PROGRAM INHIBIT SCHEME IN NAND DESIGN  
A low-current FN channel scheme for erase, program, program-inhibit and read operations is disclosed for NAND NVM memories. This invention discloses a block array architecture and 3-step half-page...
US20090196102 FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES  
A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory...
US20090175081 NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES  
A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors....
US20140241060 SUB-BLOCK DECODING IN 3D MEMORY  
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a...