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US20130250679 NAND STEP UP VOLTAGE SWITCHING METHOD  
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow...
US20140029336 SYSTEMS AND METHODS OF UPDATING READ VOLTAGES  
A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a...
US20080123405 Implanted multi-bit NAND ROM  
The market for re-programmable Non-Volatile Memory is growing very fast with the storage of pictures, movies and games. The current NAND technology for mass storage is still limited by density...
US20140313825 DRAIN SELECT GATE VOLTAGE MANAGEMENT  
Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with...
US20130329493 Natural Threshold Voltage Distribution Compaction In Non-Volatile Memory  
In a non-volatile memory system, a programming operation is performed in which faster-programming storage elements are distinguished from slower-programming storage elements. In one approach, the...
US20100074008 SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES  
Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting...
US20120039125 Nonvolatile Memory with Correlated Multiple Pass Programming  
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are...
US20110019471 Nonvolatile Memory with Correlated Multiple Pass Programming  
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are...
US20080304317 SOLID STATE MEMORY UTILIZING ANALOG COMMUNICATION OF DATA VALUES  
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices...
US20140334228 LINEARLY RELATED THRESHOLD VOLTAGE OFFSETS  
Threshold voltage offsets for threshold voltages are determined. The threshold voltage offsets may be linearly related by a non-zero slope. The threshold voltages are shifted using their...
US20140218436 CIRCUIT THAT SELECTS EPROMS INDIVIDUALLY AND IN PARALLEL  
An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a...
US20100014349 PROGRAMMING NON-VOLATILE STORAGE USING BINARY AND MULTI-STATE PROGRAMMING PROCESSES  
A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary...
US20100074012 Least significant bit page recovery method used in multi-level cell flash memory device  
A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device is provided. The method includes setting first through nth LSB page groups (n being a...
US20090161425 METHOD OF DETERMINING A FLAG STATE OF A NON-VOLATILE MEMORY DEVICE  
In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n...
US20140369118 CONFIGURING STORAGE CELLS  
Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes determining a usage history for a set of storage cells of a solid-state...
US20140056068 CONFIGURING STORAGE CELLS  
Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes determining a usage history for a set of storage cells of a solid-state...
US20060221686 INTEGRATED CIRCUIT THAT USES A DYNAMIC CHARACTERISTIC OF THE CIRCUIT  
An integrated circuit has a first component that has a dynamic characteristic that varies among like integrated circuits, for example, among integrated circuits fabricated using the same...
US20130135929 METHOD OF PROGRAMMING MULTI-LEVEL CELLS IN NON-VOLATILE MEMORY DEVICE  
A method of programming a multi-level cells (MLC) commonly coupled to a word line in a non-volatile memory device includes shadow-programming first MLC to a first shadow state, shadow-programming...
US20120206962 METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS  
A memory chip includes memory cells storing data to be read; at least one reference cell having a reference cell current level and a reference gate voltage adjuster to adjust, for each reference...
US20120155168 NEGATIVE VOLTAGE GENERATOR, DECODER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM USING NEGATIVE VOLTAGE  
A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage,...
US20110007566 MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE  
Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming...
US20150078081 Trimmable Reference Generator For Sense Amplifier  
A trimmable current reference generator for use in a sense amplifier is disclosed
US20110026325 METHOD OF PROGRAMMING A MULTI LEVEL CELL  
A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the...
US20070147114 SEMICONDUCTOR MEMORY SYSTEM  
A semiconductor memory system includes: a non-volatile semiconductor memory device; and a memory controller configured to execute operation control of the non-volatile semiconductor memory device,...
US20080037321 Partial-Write-Collector Algorithm for Multi Level Cell (MLC) Flash  
A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a...
US20150162086 Systems and Methods for Partial Page Programming of Multi Level Cells  
Multiple bits of data are programmed together to each cell of a segment of a word line while other segments of the same word line are unprogrammed. Subsequently, additional segments are similarly...
US20110280068 JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE  
Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A...
US20100074009 QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL  
Flash memory systems and methodologies are provided herein for facilitating single logical cell erasure and quad or more bit storage in a flash device. The single logical cell erasure can be...
US20130279250 NONVOLATILE MEMORY DEVICE WITH FLAG CELLS AND USER DEVICE INCLUDING THE SAME  
A nonvolatile memory device includes a flag cell configured to store flag information, a plurality of dummy cells adjacent to the flag cell, and program control logic configured to control a...
US20150131376 THRESHOLD ESTIMATION USING BIT FLIP COUNTS AND MINIMUMS  
A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a...
US20120155166 Alternate Page By Page Programming Scheme  
An alternate page by page scheme for the multi-state programming of data into a non-volatile memory is presented. Pages of data are written a page at a time onto word lines of the memory. After...
US20140254265 Flash Memory Cells, NAND Cell Units, Methods of Forming NAND Cell Units, and Methods of Programming NAND Cell Unit Strings  
Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate...
US20100128529 NAND STEP VOLTAGE SWITCHING METHOD  
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow...
US20120314495 APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB  
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as...
US20110134693 APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB  
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as...
US20100074006 DYNAMIC ERASE STATE IN FLASH DEVICE  
Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of...
US20070183194 CONTROLLING ACCESS TO DEVICE-SPECIFIC INFORMATION  
A method for providing access to device-specific information includes providing a first value to the device, and then, in the device, using a second value that is a first one-way function of the...
US20120120726 VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE FOR NON-VOLATILE STORAGE  
Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage...
US20110007562 Dynamic wordline start voltage for nand programming  
The present invention discloses a method of programming an MLC NAND flash memory device comprising: selecting a start value for a program voltage for a lower page; incrementing said program...
US20140177335 NONCONSECUTIVE SENSING OF MULTILEVEL MEMORY CELLS  
The present disclosure includes apparatuses and methods for nonconsecutive sensing of multilevel memory cells. A number of methods include sensing a unit of information from a multilevel memory...
US20110242889 PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE  
Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage...
US20110222338 METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS  
A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference...
US20100074005 EEPROM EMULATION IN FLASH DEVICE  
Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two...
US20140126286 SINGLE-LEVEL CELL ENDURANCE IMPROVEMENT WITH PRE-DEFINED BLOCKS  
Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel...
US20090240872 MEMORY DEVICE WITH MULTIPLE-ACCURACY READ COMMANDS  
A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first...
US20060221684 Printing apparatus and control program updating method  
A printing apparatus which obtains, through a network, updating data for an updating process to update a control program for executing a printing process on the basis of print data has: a...
US20140347928 LOW DISTURBANCE, POWER-CONSUMPTION, AND LATENCY IN NAND READ AND PROGRAM-VERIFY OPERATIONS  
A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge...
US20130155769 Non-Volatile Memory And Method With Improved First Pass Programming  
A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The...
US20120039121 PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE  
Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the...
US20120033494 DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE  
A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine...