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US20090310424 METHOD OF ERASING A FLASH EEPROM MEMORY  
The invention is a new method for erasing a flash EEPROM memory device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the...
US20090296463 MEMORY CELLS, MEMORY DEVICES AND INTEGRATED CIRCUITS INCORPORATING THE SAME  
A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to...
US20090273962 FOUR-TERMINAL MULTIPLE-TIME PROGRAMMABLE MEMORY BITCELL AND ARRAY ARCHITECTURE  
Embodiments disclosed herein relate to a non-volatile memory bitcell and arrays thereof, methods of detecting whether the bitcell is in a programmed state, methods of detecting whether the bitcell...
US20090268508 Reverse leakage reduction and vertical height shrinking of diode with halo doping  
One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different...
US20090268524 THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY  
In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a...
US20090268523 THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY  
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has...
US20090251959 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF  
A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and...
US20090251958 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same  
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store...
US20090249167 Semiconductor memory device  
A semiconductor memory device includes a data storage area wherein a plurality of data cells, respectively storing one bit of data, is arranged in a lattice form, a redundant data storage area that...
US20090219743 Three dimensional structure memory  
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately...
US20090219763 NON-VOLATILE MEMORY  
A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the...
US20090213643 Integrated Circuit and Method of Improved Determining a Memory State of a Memory Cell  
According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first...
US20090207654 Semiconductor device including plurality of parallel input/output lines and methods of fabricating and using the same  
Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality...
US20090207655 MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE  
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating...
US20090196096 Memory Cells, Methods Of Forming Memory Cells, And Methods Of Forming Programmed Memory Cells  
In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing...
US20090185413 SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT WITH OUTPUT PATH CONTROL UNIT  
A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes...
US20090175073 Nanostructure-Based Memory  
Improved memory devices that include one or more nanostructures such as carbon nanotubes or other nanostructures, as well as systems and devices incorporating such improved memory devices, are...
US20090175064 SEMICONDUCTOR MEMORY DEVICE WITH REDUCED COUPLING NOISE  
A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of...
US20090129145 Memory Cell Array Comprising Floating Body Memory Cells  
A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated...
US20090122613 Non-volatile memory device and method of operating the same  
A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection...
US20090102751 MEMORY ELEMENT AND DISPLAY DEVICE  
The present invention provides a memory element includes a thin film transistor configured to have a semiconductor thin film and a pair of gate electrodes that vertically sandwich the semiconductor...
US20090103367 ONE-TRANSISTOR CELL SEMICONDUCTOR ON INSULATOR RANDOM ACCESS MEMORY  
Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be...
US20090097308 MULTIVALUE MEMORY STORAGE WITH TWO GATING TRANSISTORS  
Digital memory devices and systems, as well as methods of operating digital memory devices, that include a multivalue memory cell with a first and a second gating transistor arranged in parallel,...
US20090091972 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF  
The disclosure concerns a memory including a floating body provided in a semiconductor layer between a source and a drain and storing data; a first gate dielectric provided on a first surface of...
US20090086535 SEMICONDUCTOR ARRAY  
A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines...
US20090080236 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second...
US20090073758 SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS  
The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate...
US20090067220 Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor  
A semiconductor device has a first inverter including a drive transistor and a load transistor; a second inverter including a drive transistor and a load transistor, a transmission transistor...
US20090059678 Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device  
In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory...
US20090052258 Systems, methods and devices for a memory having a buried select line  
Embodiments are described for programming and erasing a memory cell by utilizing a buried select line. A voltage potential may be generated between a source-drain region and the buried select line...
US20090048819 Multiple-type memory  
A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to...
US20090034327 THERMAL-EMITTING MEMORY MODULE, THERMAL-EMITTING MODULE SOCKET, AND COMPUTER SYSTEM  
The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module...
US20090003050 FLOATING BODY MEMORY ARRAY  
Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other...
US20090003051 Semiconductor Memory Device and Semiconductor Device  
The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose...
US20090003030 METHODS FOR FERROELECTRIC DOMAIN READING  
Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material...
US20080316831 Nonvolatile semiconductor device, system including the same, and associated methods  
A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the...
US20080298125 SEMICONDUCTOR DEVICE  
A semiconductor device includes a semiconductor substrate including an element region which is surrounded by an element isolation insulation layer, a transistor including a gate electrode which is...
US20080285337 RECORDABLE ELECTRICAL MEMORY  
A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon...
US20080266944 NON-VOLATILE MEMORY CELL WITH A HYBRID ACCESS TRANSISTOR  
A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The...
US20080266935 DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE  
In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a...
US20080259680 Memory Element and Method for Manufacturing Same  
A novel nonvolatile memory element, which can be manufactured by a simple and high yield process by using an organic material and has a high on/off ratio, and a method for manufacturing such...
US20080253179 SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATING THE SAME  
A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree...
US20080239799 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE/WRITE METHOD THEREOF  
A nonvolatile semiconductor memory device includes a memory cell array which includes a memory cell string including a plurality of memory cells each having a variable resistor element and a...
US20080230763 Metallic Nanospheres Embedded in Nanowires Initiated on Nanostructures and Methods for Synthesis Thereof  
A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there...
US20080219044 Read Disturb Reduction Circuit for Spin Transfer Torque Magnetoresistive Random Access Memory  
Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read...
US20080198649 Memory device and method of manufacturing a memory device  
A memory device includes a bit line, a reading word line, a bit line contact, an electrode, a writing word line and a contact tip. The bit line is formed on a substrate. The reading word line is...
US20080192535 Sense amplifiers and semiconductor devices including the same  
A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second...
US20080180994 MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SAME  
A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select...
US20080165577 Semiconductor device  
A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect...
US20080165588 RESET METHOD OF NON-VOLATILE MEMORY  
A reset method of a non-volatile memory is described. The non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each including a portion of the substrate, a...
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