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US20130301343 THRESHOLD VOLTAGE MEASUREMENT DEVICE  
A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating...
US20110026309 SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL  
A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at...
US20110075470 EMBEDDED SRAM STRUCTURE AND CHIP  
An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at...
US20150213873 INJECTION-LOCKED PHASE LOCKED LOOP CIRCUITS USING DELAY LOCKED LOOPS  
An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a...
US20120106237 BOOST CIRCUIT FOR GENERATING AN ADJUSTABLE BOOST VOLTAGE  
A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also...
US20140169077 OPERATION AWARE AUTO-FEEDBACK SRAM  
A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes...
US20130028007 SENSE AMPLIFIER  
Embodiments of the invention provide a sense amplifier, a SRAM chip comprising the sense amplifier and a method for conducting read operation on a SRAM cell. The sense amplifier according to an...
US20150131366 VOLTAGE CONTROLLER  
A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage...
US20130279241 CIRCUITS AND METHODS FOR REDUCING MINIMUM SUPPLY FOR REGISTER FILE CELLS  
A register file employing a shared supply structure to improve the minimum supply voltage.
US20130088913 CIRCUIT AND METHOD OF WORD LINE SUPPRESSION  
A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging...
US20150168982 LEAKAGE-AWARE VOLTAGE REGULATION CIRCUIT AND METHOD  
A voltage regulation circuit and method where a pre-charge device (PCD) and a power gate device (PGD) are connected to a voltage line that supplies power to at least one additional device. The PCD...
US20130223136 SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor  
The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up...
US20130100731 INDEPENDENTY-CONTROLLED-GATE SRAM  
The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and...
US20150029783 METHOD OF DETECTING TRANSISTORS MISMATCH IN A SRAM CELL  
The present invention provides a method of detecting the transistor mismatch in a SRAM cell. The SRAM cell comprises two pass-gate transistors and a bi-stable circuit including two pull up...
US20130058155 SRAM DIMENSIONED TO PROVIDE BETA RATIO SUPPORTING READ STABILITY AND REDUCED WRITE TIME  
A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup...
US20140293679 MANAGEMENT OF SRAM INITIALIZATION  
An embodiment of the current disclosure is directed to a Static Random Access Memory (SRAM) device, and a design structure for the SRAM device. The SRAM device may include one or more SRAM cells....
US20150055389 SELF-TIMED, SINGLE-ENDED SENSE AMPLIFIER  
An integrated circuit including a sense amplifier connected to a sense line is provided. The sense amplifier is configured to end a precharge phase of the sense line based on a state of the sense...
US20150103584 CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING  
A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay...
US20130064004 SRAM CELL WRITABILITY  
Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a...
US20110002168 Binary Logic Utilizing MEMS Devices  
Embodiments disclosed herein generally relate to switches that utilize micro-electromechanical systems (MEMS). By replacing transistors in many devices with switches such as MEMS switches, the...
US20120075918 SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell Stability and Design Structure for Same  
An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that...
US20140003133 SRAM LAYOUTS  
Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a...
US20140254246 Dual-port SRAM Systems  
Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a...
US20140036578 SRAM READ PREFERRED BIT CELL WITH WRITE ASSIST CIRCUIT  
Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second...
US20140269023 BIASING BULK OF A TRANSISTOR  
A circuit comprises a first transistor of a first type, a second transistor of a second type, and a third transistor of the first type or the second type. The first transistor and the second...
US20140247652 PROCESS TOLERANT CIRCUITS  
Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from...
US20130107610 SRAM CELL WITH INDIVIDUAL ELECTRICAL DEVICE THRESHOLD CONTROL  
A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of...
US20130003443 8T SRAM CELL WITH HIGHER VOLTAGE ON THE READ WL  
The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the...
US20120014171 SCHMITT TRIGGER-BASED FINFET SRAM CELL  
The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new...
US20130121065 DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM  
A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair...
US20150036417 SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN  
A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is...
US20130003446 Method for Extending Word-Line Pulses  
An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of...
US20130182494 SKEWED SRAM CELL  
A memory cell including a cross-coupled latch with corresponding storage nodes, and further including first and second write pass gate transistors and first and second read pass gate transistors....
US20120075919 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability  
Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and...
US20140355334 HANDSHAKING SENSE AMPLIFIER  
Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also...
US20140092674 Circuits and Methods of a Self-Timed High Speed SRAM  
Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near...
US20100322026 MECHANISM FOR MEASURING READ CURRENT VARIABILITY OF SRAM CELLS  
A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The...
US20120281458 ULTRA LOW POWER SRAM CELL CIRCUIT WITH A SUPPLY FEEDBACK LOOP FOR NEAR AND SUB THRESHOLD OPERATION  
An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The...
US20130201753 IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM  
A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided....
US20120195108 SRAM CELL HAVING A P-WELL BIAS  
A process of performing an SRAM single sided write operation including applying a positive bias increment to an isolated p-well containing a passgate in an addressed SRAM cell. A process of...
US20140119101 WORDLINE TRACKING FOR BOOSTED-WORDLINE TIMING SCHEME  
Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided....
US20100039853 Design Structure, Structure and Method of Using Asymmetric Junction Engineered SRAM Pass Gates  
A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through...
US20120140551 STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL  
A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost...
US20150003147 SRAM RESTORE TRACKING CIRCUIT AND METHOD  
novel and useful SRAM restore tracking circuit adapted to improve the tracking of SRAM cell behavior for different PVT corners. The SRAM array access path is mainly influenced by two stages: (1)...
US20080239792 METAL SILICIDE ALLOY LOCAL INTERCONNECT  
A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material...
US20130083591 Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets  
An integrated circuit memory is disclosed in which an array of 8 T SRAM cells is arranged in rows and columns using a plurality of write wordlines for each row of 8 T SRAM cells to control write...
US20140078817 INTEGRATED CIRCUITS WITH SRAM CELLS HAVING ADDITIONAL READ STACKS AND METHODS FOR THEIR FABRICATION  
Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an...
US20150194208 SRAM WORDLINE DRIVER SUPPLY BLOCK WITH MULTIPLE MODES  
A wordline driver supply block supporting multiple operation modes of a memory of a microprocessor in a device for reducing power consumption thereof.
US20150262707 DESIGN-FOR-TEST APPARATUSES AND TECHNIQUES  
Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell,...
US20150029782 WIDE RANGE MULTIPORT BITCELL  
A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the...