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US20140078815 VOLTAGE RAIL NOISE SENSING CIRCUIT AND METHOD  
Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail noise can be determined. The actual...
US20120218811 Circuit  
An object of the current invention is to provide DRAM that is not limited by capacitors.
US20100296329 Differential Plate Line Screen Test for Ferroelectric Latch Circuits  
Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled...
US20110157962 BIAS SENSING IN DRAM SENSE AMPLIFIERS THROUGH VOLTAGE-COUPLING/DECOUPLING DEVICE  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
US20120195102 NANO-ELECTRO-MECHANICAL DRAM CELL  
A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.
US20080291717 SEMICONDUCTOR STORAGE DEVICE INCORPORATED INTO A SYSTEM LSI WITH FINER DESIGN RULES  
In the present invention, a row decoder circuit is made up of a transistor having a first gate oxide film thickness, a transistor having a second gate oxide film thickness, and a transistor having...
US20120063202 3T DRAM CELL WITH ADDED CAPACITANCE ON STORAGE NODE  
A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a...
US20080144358 Read state retention circuit and method  
A read state retention circuit and method are disclosed. The read state retention circuit comprises a charge storage unit, charging unit, sensing circuit and state indicator. The charging circuit...
US20100309710 Variable Impedance Circuit Controlled by a Ferroelectric Capacitor  
A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization...
US20130170286 DECOUPLING CAPACITANCE CALIBRATION DEVICES AND METHODS FOR DRAM  
A decoupling capacitance (decap) calibration device includes a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power...
US20090257272 REDUCED SIZE CHARGE PUMP FOR DRAM SYSTEM  
A memory system includes: a memory array, comprising a plurality of memory banks, respectively enabled by a plurality of bank enable signals; a bank selector circuit, for generating the plurality...
US20130272054 SYSTEM FOR POWERING UP VOLTAGE DOMAINS AFTER EXITING POWERDOWN EVENT  
A system for charging a low voltage power domain in a low power DRAM includes: a first capacitor, for providing a local domain power voltage supply; a first transistor, coupled to the first...
US20090244954 STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS  
A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including...
US20140269009 DRAM WITH PULSED SENSE AMP  
Disclosed is a pulsed sense amplifier approach for resolving data on a bit line.
US20090080234 SEMICONDUCTOR DEVICE AND DRAM CONTROLLER  
According to a semiconductor device of the present invention, a differential potential between a sense amplification level and a precharge level of a sense amplifier is set to a power supply...
US20100202190 COMPACT AND HIGHLY EFFICIENT DRAM CELL  
A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC...
US20120039114 Memcapacitor  
A memcapacitor device (100) includes a first electrode (104) and a second electrode (106) and a memcapacitive matrix (102) interposed between the first electrode (104) and the second electrode...
US20090257273 2T SRAM CELL STRUCTURE  
A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word...
US20130314123 LOOKUP TABLE AND PROGRAMMABLE LOGIC DEVICE INCLUDING LOOKUP TABLE  
A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of...
US20110273921 INTEGRATABLE PROGRAMMABLE CAPACITIVE DEVICE  
A circuit with a capacitive device is disclosed. The circuit may comprise a capacitive device connected between a first conductor and a second conductor. The capacitive device may comprise a first...
US20130051126 CAPACITORS, APPARATUS INCLUDING A CAPACITOR AND METHODS FOR FORMING A CAPACITOR  
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a...
US20110188295 High Performance eDRAM Sense Amplifier  
Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each...
US20080266935 DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE  
In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a...
US20140119099 DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS  
A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control...
US20090251946 DATA CELLS WITH DRIVERS AND METHODS OF MAKING AND OPERATING THE SAME  
Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a...
US20080310236 Subtraction circuits and digital-to-analog converters for semiconductor devices  
A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be...
US20100054024 CIRCUIT FOR READING A CHARGE RETENTION ELEMENT FOR A TIME MEASUREMENT  
A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and...
US20080084731 DRAM devices including fin transistors and methods of operating the DRAM devices  
A dynamic random access memory (DRAM) device may include: a semiconductor substrate including an active fin, an active region, and an isolation layer; one or more cell gate structures on a central...
US20100054038 PROGRAMMING OF A CHARGE RETENTION CIRCUIT FOR A TIME MEASUREMENT  
A method of controlling an electronic charge retention circuit for time measurement, including at least a first capacitive element, the dielectric of which has a leakage, and at least a second...
US20120014170 Capacitive Crossbar Arrays  
A capacitive crossbar array (100) includes a first set of conductors (102) and a second set of conductors (104) which intersect to form crosspoints. A nonlinear capacitive device (106) is...
US20080013365 HIGH EFFICIENCY PORTABLE ARCHIVE  
A high efficiency portable archive implements a storage system running on a virtualization layer to archive point-in-time versions of a raw data set and the storage system itself as a virtual...
US20070297214 Semiconductor device  
To provide a semiconductor device in which power consumption at the time of an anti-collision operation is reduced. A semiconductor device includes an arithmetic circuit, a storage device, and...
US20100118596 Embedded DRAM with bias-independent capacitance  
An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel...
US20060120138 Semiconductor memory with volatile and non-volatile memory cells  
The present invention relates to a semiconductor memory with a volatile memory device, in particular a DRAM memory device, and with a non-volatile memory device. The volatile memory device is...
US20080094877 FASTER INITIALIZATION OF DRAM MEMORY  
A method of initializing dynamic random access memory (DRAM) comprises allocating one or more rows of a plurality of cells in the DRAM; signaling an initialization request to initialize the...
US20150043269 ELECTRIC CHARGE FLOW CIRCUIT FOR A TIME MEASUREMENT  
A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.
US20100097840 FRAM including a tunable gain amp as a local sense amp  
FRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a...
US20100157660 MULTIPLE-VALUED DRAM  
Provided herein is an MV DRAM device capable of storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to...
US20150054666 CURRENT MEMORY CELL AND A CURRENT MODE DIGITAL-TO-ANALOG CONVERTER INCLUDING THE SAME  
A current memory cell includes an amplifier, transistor, first and second capacitors, and first to third switching units. The amplifier includes first to third terminals. The transistor is coupled...
US20100073994 LEAKAGE COMPENSATION CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS  
A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell...
US20100002488 F-SRAM Margin Screen  
A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes...
US20070081379 Write assist for latch and memory circuits  
One embodiment provides a system to assist setting a state of a latch system. The system includes a latch system connected to a node, the latch system residing in one of a first state and a second...
US20110080771 DRAM POSITIVE WORDLINE VOLTAGE COMPENSATION DEVICE FOR ARRAY DEVICE THRESHOLD VOLTAGE AND VOLTAGE COMPENSATING METHOD THEREOF  
The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a...
US20110188287 High speed FRAM including a deselect circuit  
High speed FRAM including a deselect circuit is realized for replacing SRAM, wherein the deselect circuit is connected to a local bit line pair for forcing a middle voltage to storage nodes of...
US20140219007 DRAM WITH SEGMENTED PAGE CONFIGURATION  
This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which...
US20100054023 CHARGE STORAGE CIRCUIT, VOLTAGE STABILIZER CIRCUIT, METHOD FOR STORING CHARGE USING THE SAME  
A charge storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a corresponding word line among the word lines and connected to...
US20090059648 FERROELECTRIC SEMICONDUCTOR STORAGE DEVICE  
This ferroelectric semiconductor storage device includes: a ferroelectric capacitor; and a transistor having one end of its current path connected to one electrode of the ferroelectric capacitor....
US20080130350 DRAM WITH METAL-LAYER CAPACITORS  
In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a substrate including a plurality of access transistors, and a plurality of storage capacitors corresponding...
US20090097301 SEMICONDUCTOR STORAGE APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT INCORPORATING THE SAME  
An object is to provide a semiconductor memory device which can dynamically change the number of memory cells used as by-pass capacitors. In each memory block, one selector signal line is provided...
US20120057395 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit includes a cell block including a plurality of cell mats having a plurality of word lines and a plurality of bit lines perpendicular to the plurality of word...

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