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US20120127187 |
Error Check-Only Mode
Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes...
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US20110169848 |
Parameter FIFO
A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings...
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US20080049036 |
Multimedia Playback System, FIFO Memory System, and Method for Storing Multimedia Data
A multimedia playback system, a FIFO memory system, and a method for storing multimedia data are provided. The multimedia playback system or the FIFO system comprises a FIFO memory and a memory...
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US20080055327 |
Highly Efficient Display FIFO
A graphics controller including a display pipe and a first-in-first-out (FIFO) buffer within the display pipe is provided. The FIFO buffer stores pixel data representing an image for display. The...
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US20060103659 |
Latency tolerant system for executing video processing operations
A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar...
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US20090289948 |
DISPLAY DEVICE AND METHOD FOR CONTROLLING BACKLIGHT THEREOF
A display device having backlight and the backlight control method thereof is provided. Through the provided method, it is capable of fast determining which intensity range the intensity signal...
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US20060022985 |
Preemptive rendering arbitration between processor hosts and display controllers
A system comprises a display controller adapted to monitor a first-in, first-out module (“FIFO”) data level, a memory controller coupled to said display controller, and a memory coupled to said dis...
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US20080143733 |
Systems and Methods for Providing a Shared Buffer in a Multiple FIFO Environment
Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial processing...
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US20100271542 |
Stroke-to-raster video conversion method having error correction capabilities
Methods of performing stroke-to-raster video conversion having leading-edge error correction and/or falling-edge error correction are provided. Incoming data is pipelined before being written into...
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US20070182750 |
Drawing apparatus and method for processing plural pixels in parallel
A drawing apparatus includes a reception unit, a first holding unit and a drawing processing unit. The reception unit receives graphic information. The first holding unit holds a plurality of first...
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US20100073388 |
UNIFIED MEMORY ARCHITECTURE AND DISPLAY CONTROLLER TO PREVENT DATA FEED UNDER-RUN
A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and...
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US20080192061 |
System for response speed compensation in liquid crystal display using embedded memory device and method of controlling frame data of image
Provided are a system for compensating response speed and a method of controlling frame data of an image. The system includes: a circuit for compensating response speed; an internal frame memory...
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US20080252649 |
Self-Automating Bandwidth Priority Memory Controller
A memory controller that includes a write first in first out (FIFO) region of the memory for receiving pixel data and a read FIFO region of the memory for accessing the pixel data received through...
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US20120007875 |
Multiple Monitor Video Control
A computer system comprising a processor including a display controller operative to output display data and a clock signal, and a programmable logic device communicatively connected to the...
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US20100238186 |
Display Controllers Including Memory Controllers
A display controller is provided. The display controller includes an external memory and a timing controller which compresses current frame data to generate front first in-first out (FIFO) input...
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US20100149121 |
SYSTEM AND METHOD FOR INTERFACING APPLICATIONS PROCESSOR TO TOUCHSCREEN DISPLAY FOR REDUCED DATA TRANSFER
System and method for substantially reducing an involvement of an applications processor in receiving data from a touchscreen display. In one aspect, the system includes a controller may be...
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US20100134504 |
ELECTROPHORESIS DISPLAY
An electrophoresis display is provided to reduce writing time of a memory. The electrophoresis display includes: an electrophoresis display panel; a first memory and a second memory for...
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US20100128059 |
Decompression system and method for DCT-base compressed graphic data with transparent attribute
A decompression system for DCT-base compressed graphic data with transparent attribute includes a memory to store a compressed graphic data and a compressed mask data; a controller to read the...
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US20100123728 |
MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM
A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and...
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US20120147024 |
DATA PACKER FOR PACKING AND ALIGNING WRITE DATA
A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More...
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US20120133661 |
DISPLAY DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME
A display driving circuit includes a clock dividing unit and a data processing unit. The clock dividing unit receives a first clock signal, generates a second clock signal having a second clock...
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US20120081381 |
DISPLAY DRIVE DEVICE, DISPLAY DEVICE, DRIVING CONTROL METHOD, AND ELECTRONIC DEVICE
display drive device includes a correction data memory circuit, a data reading control circuit, and an image data correction circuit. The correction data memory circuit stores a plurality of pieces...
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US20110141128 |
METHOD AND APPARATUS FOR PROCESSING A USER INTERFACE IN AN IMAGE PROCESSOR
A method and apparatus for processing a user interface in an image processor are provided. In the method, at least one Region of Interest (ROI) is set on an image displayed on a screen. Location...
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US20100315556 |
IMAGE PROCESSING CIRCUIT AND METHOD THEREOF
An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, a plurality of line buffers, a first sharpness circuit, a second...
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