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US20120200347 SKEWED PLACEMENT GRID FOR VERY LARGE SCALE INTEGRATED CIRCUITS  
A skewed placement grid for an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a placement grid which includes a plurality of cells. Each of the plurality of cells includes...
US20140139271 INTEGRATED CIRCUIT HAVING STACK STRUCTURE  
Provided is an integrated circuit (IC) having a stacked structure. The IC includes: a first IC having a power input terminal to which a power supply voltage is applied; and a second IC having a...
US20120286858 Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells  
An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of...
US20150168973 STACKED CHIPS POWERED FROM SHARED VOLTAGE SOURCES  
A system includes multiple integrated circuits (ICs), each with a high supply level input and a low supply level input. With respect to the topology of these power connections, the ICs are...
US20140097892 DOUBLE PATTERNING COMPATIBLE COLORLESS M1 ROUTE  
A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and...
US20150179240 SHARING RESOURCES IN MULTI-DICE STACKS  
Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided....
US20130049840 IMPLEMENTING DIFFERENTIAL RESONANT CLOCK WITH DC BLOCKING CAPACITOR  
A method and circuit for implementing differential resonant clocking with a DC blocking capacitor, and a design structure on which the subject circuit resides are provided. An on-chip inductor and...
US20110095816 NETWORK ON CHIP BUILDING BRICKS  
The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal...
US20140253228 INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION  
An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the...
US20090015185 Semiconductor Module, and Hybrid Vehicle Drive Device Including the Same  
A bus bar constitutes a power line and another bus bar constitutes an earth line. The bus bars are layered in the normal direction of an insulating substrate via an insulating member. Here, the...
US20130162346 INTERCONNECTION DEVICE IN A MULTI-LAYER SHIELDING MESH  
An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage...
US20150130534 INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK  
Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.
US20130293292 INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK  
Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.
US20100164614 Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules  
An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly...
US20110012673 INTEGRATED CIRCUIT INCLUDING A LARGE NUMBER OF IDENTICAL ELEMENTARY CIRCUITS POWERED IN PARALLEL  
The invention relates to an integrated circuit comprising a succession of N identical elementary circuits, juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to...
US20090015322 Integrated circuit with multiple layers of circuits  
An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and...
US20070103228 STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD  
A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically...
US20150028940 INTEGRATED CIRCUIT HAVING AT LEAST ONE FUNCTIONAL CIRCUIT BLOCK OPERATING IN MULTI-SOURCE POWER DOMAIN AND RELATED SYSTEM WITH POWER MANAGEMENT  
An integrated circuit has a semiconductor layer, at least one metal layer, a plurality of functional circuit blocks formed on the semiconductor layer, and a power mesh formed on the at least one...
US20150160975 VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM  
The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically...
US20110050335 LOW-CAPACITANCE ELECTROSTATIC DISCHARGE PROTECTION DIODES  
A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to...
US20110063012 CIRCUIT ARRANGEMENT  
A circuit arrangement is provided. The circuit arrangement includes a first transistor, a second transistor, a third transistor, and a fourth transistor respectively comprising a first terminal, a...
US20140266418 Stacked Chip System  
A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first...
US20150008979 ACTIVE PEN IC WITH A REDUCED AMOUNT OF PADS AND A METHOD THEREOF  
An active pen IC includes a plurality of pads coupled to receive a plurality of receive (RX) signals induced from a mobile device, the received RX signals constituting an original group of RX...
US20120049948 Abutment structure of semiconductor cell  
An abutment structure comprises a power rail, a ground rail parallel to the power rail, first cells and second cells. An area is defined between the power and the ground rails. A portion of each...
US20130154727 DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS  
A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then...
US20120014024 Method of Testing a Structure Protected from Overvoltages and the Corresponding Structure  
An electronic device includes an electronic component and a protection circuit configured to protect the component from overvoltages. A control circuit is configured to inhibit a part of the...
US20130265840 SEMICONDUCTOR DEVICE HAVING AUXILIARY POWER-SUPPLY WIRING  
Disclosed herein is a semiconductor device that includes a signal wiring arranged on a first layer and extending over the circuit block or blocks in the first direction so as to reach the first...
US20140266408 Circuit and Method for a Multi-Mode Filter  
An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first...
US20090251206 INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME  
An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver...
US20090115504 CIRCUIT DESIGN METHODOLOGY TO REDUCE LEAKAGE POWER  
A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and...
US20100295607 SYSTEM AND METHOD TO REDUCE NOISE IN A SUBSTRATE  
A system for reducing noise in a chip is disclosed and may include a substrate, a first well disposed on top of the substrate, a second well and a third well that are both disposed within the...
US20130162344 DISTRIBUTED LC RESONANT TANKS CLOCK TREE SYNTHESIS  
A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor...
US20130057339 Circuit and Electronic Module for Automatic Addressing  
An integrated circuit includes a first configuration terminal, a second configuration terminal, a bus terminal, and an auto addressing circuit coupled to the first and second configuration...
US20150022262 COMPLETE SYSTEM-ON-CHIP (SOC) USING MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) TECHNOLOGY  
Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology....
US20120256683 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of...
US20110102076 Semiconductor integrated circuit  
A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of...
US20150158114 PHASE CORRECTOR FOR LASER TRIMMING, AN INTEGRATED CIRCUIT INCLUDING SUCH A PHASE CORRECTOR, AND A METHOD OF PROVIDING PHASE CORRECTION IN AN INTEGRATED CIRCUIT  
A phase corrector for laser trimming a component, the phase corrector comprising: a first correction structure located to a first side of the component, the first correction structure comprising...
US20110102014 THREE DIMENSIONAL INTEGRATED CIRCUITS  
A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer,...
US20140218102 INTEGRATED CIRCUIT  
An integrated circuit (IC) including a high-speed signal input pin, a common node, a high-speed signal output pin, and a core circuit is provided. The high-speed signal input pin and the...
US20100277232 HYBRID MICROSCALE-NANOSCALE NEUROMORPHIC INTEGRATED CIRCUIT  
Embodiments of the present invention include hybrid microscale-nanoscale neuromorphic integrated circuits that include an array of analog computational cells fabricated on an...
US20110109381 Integrated Circuit Die Stacks With Rotationally Symmetric Vias  
An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the...
US20120081984 THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT  
Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave...
US20140312878 METHOD FOR INDEXING DIES COMPRISING INTEGRATED CIRCUITS  
Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage...
US20140176234 APPARATUSES AND METHODS OF COMMUNICATING DIFFERENTIAL SERIAL SIGNALS INCLUDING CHARGE INJECTION  
Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an...
US20130009275 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TERMINAL STRUCTURE OF STANDARD CELL  
A semiconductor integrated circuit device includes a first standard cell and a second standard cell adjacent to the first standard cell in a first direction. An interconnect is provided to extend...
US20100265751 MULTI-CHIP PACKAGES PROVIDING REDUCED SIGNAL SKEW AND RELATED METHODS OF OPERATION  
A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line...
US20150008954 MONOLITHIC INTEGRATED CIRCUIT DIE HAVING MODULAR DIE REGIONS STITCHED TOGETHER  
An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions...
US20100327966 SEMICONDUCTOR DEVICE HAVING CIRCUIT BLOCKS WITH MUTUALLY THE SAME CIRCUIT CONFIGURATION  
To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to...
US20070284610 Switching Device, Drive And Manufacturing Method For The Same, Integrated Circuit Device And Memory Device  
Provided is a switching device including ion conducting part 4 having an ion conductor, first electrode 1 formed at a first gap away from ion conducting part 4, second electrode 2 formed to be in...
US20110001509 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR TESTING THE SAME  
A semiconductor integrated circuit device includes: terminals 11a and 11m; first to (2n+1)-th resistive elements (n is an integer of at least 1) (resistive element group 12) connected in series...

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