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US20090289677 |
DEVICE
A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by...
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US20090289676 |
DLL circuit
A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an...
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US20090289675 |
DIFFERENTIAL TRANSMITTER AND AUTO-ADJUSTMENT METHOD OF DATA STROBE THEREOF
A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe...
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US20090289673 |
VOLTAGE CONTROLLED OSCILLATORS AND PHASE-FREQUENCY LOCKED LOOP CIRCUIT USING THE SAME
A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay...
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US20090284291 |
COMPLEMENTARY SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE COMPRISING SAME
A complementary signal generation circuit includes a first transmission path including a first number N of inverters and a second transmission path including a second number (N−1) of inverters. A...
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US20090284290 |
DLL CIRCUIT ADAPTED TO SEMICONDUCTOR DEVICE
A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses...
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US20090278581 |
DELAY LOCK LOOP AND PHASE ANGLE GENERATOR
The provided delay lock loop delaying an input signal includes a quadrature generator, a voltage controller and a delay cell. The input signal is inputted into the quadrature generator and the...
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US20090278580 |
CLOCK CONTROL CIRCUIT AND A SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME
A clock control circuit includes a clock delay device, an edge detection device, a phase determination device and a delay control device. The clock delay device generates a delayed rising clock and...
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US20090273381 |
DELAYED LOCKED LOOP CIRCUIT
A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of...
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US20090273380 |
DELAY LOCKED LOOP CIRCUIT AND METHOD THEREOF
A delayed locked loop (DLL) circuit for reducing power consumption in updating a delay value of an external clock after locking. The DLL circuit includes a phase comparator for comparing a phase of...
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US20090267665 |
SEMICONDUCTOR MEMORY DEVICE FOR GENERATING A DELAY LOCKED CLOCK IN EARLY STAGE
A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data...
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US20090267664 |
PLL CIRCUIT
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing...
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US20090267663 |
ELECTRONIC SYSTEM THAT ADJUSTS DLL LOCK STATE ACQUISITION TIME
One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and...
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US20090261877 |
Duty cycle correction circuit with wide-frequency working range
A duty cycle correction circuit with wide-frequency working range utilizes a pulse generator having adjustable pulse width function to adjust the width of the pulse and outputs a clock signal with...
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US20090256605 |
PHASE CONTROLLING APPARATUS, PHASE-CONTROL PRINTED BOARD, AND CONTROLLING METHOD
In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be...
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US20090256604 |
REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT
A register controlled DLL circuit occupies a relatively small area in a semiconductor device by reducing the number of flip-flops for generating timing pulses that are used to control a DLL...
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US20090256603 |
REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT
A register controlled delay locked loop (DLL) circuit, including: a phase comparator configured to compare phases of a source clock and a feedback clock with each other, and a clock delay circuit...
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US20090256577 |
Delay Lock Loop Circuit, Timing Generator, Semiconductor Test Device, Semiconductor Integrated Circuit, and Delay Amount Calibration Method
A method replaces a delay amount measurement in which an initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for...
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US20090251183 |
DELAY LOCK LOOP CIRCUIT AND SEMICONDUCTOR DEVICE
A simple circuit for preventing occurrence of a hazard and output delay for an asynchronous input signal in a clock signal. A flip-flop circuit (FF) outputs an output signal at a low level to a...
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US20090244995 |
Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor
A receive circuit ( 320 ) includes a DLL core ( 510 ), a latch ( 326 ), and a DLL control circuit ( 520 ). The DLL core ( 510 ) has a first input for receiving a DLL clock signal, a second input...
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US20090243679 |
Semi-Digital Delay Locked Loop Circuit and Method
A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for...
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US20090243678 |
Delay locked-loop circuit and display apparatus
A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with...
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US20090243677 |
Clock generator and methods using closed loop duty cycle correction
Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock...
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US20090230946 |
Timing generator and semiconductor test apparatus
A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew...
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US20090224807 |
JITTER REDUCTION CIRCUIT AND FREQUENCY SYNTHESIZER
The jitter reduction circuit to reduce phase noise in a pulse train, comprises: —a resettable integrator ( 70 ) to integrate the pulse train, —a comparator ( 72 ) to compare the integrated...
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US20090219069 |
Semiconductor integrated circuit device
Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic...
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US20090219068 |
Phase detector, phase comparator, and clock synchronizing device
A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock...
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US20090206898 |
Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL....
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US20090206897 |
SKEW ADJUSTMENT CIRCUIT AND A METHOD THEREOF
Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output...
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US20090206896 |
DELAY LOCKED LOOP
An integrated circuit includes a chain of delay elements, a first phase detector, and a controller. The chain of delay elements is configured to delay an input clock signal for providing an output...
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US20090206884 |
LOCKING STATE DETECTOR AND DLL CIRCUIT HAVING THE SAME
A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to...
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US20090201059 |
System and Method for Signal Adjustment
Embodiment of the present invention relate to a method for receiving a first signal, determining a first characteristic of the first signal, the characteristic being a time based characteristic,...
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US20090195277 |
SEMICONDUCTOR INTEGRATED CIRCUIT
The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock...
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US20090189658 |
DLL circuit, semiconductor device using the same, and method for controlling DLL circuit
There is provided a DLL circuit that uses a small amount of area on a chip, and is compatible with a wide range of clock frequencies. The DLL circuit has a delay line 210 for delaying an external...
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US20090189657 |
Delay locked loop circuit and method for eliminating jitter and offset therein
A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one...
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US20090189656 |
Delay-locked loop and a stabilizing method thereof
A delay-locked loop includes a phase detector, a shift register, a digital low pass filter, a digital to analog converter, a bias circuit, and a delay circuit. The phase detector generates a...
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US20090189655 |
PHASE-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT
A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference...
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US20090184741 |
Delay lock loop circuit, phase lock loop circuit, timing generator, semiconductor tester and semiconductor integrated circuit
A delay lock loop circuit and a phase lock loop circuit are designed to reduce a lock-up time, extend a lock range without increasing the number of bits of a counter, and quickly return to a lock...
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US20090179675 |
DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME
A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback...
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US20090174447 |
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME
A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to...
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US20090168942 |
Apparatus and method for frequency synthesis using delay locked loop
An apparatus and method for frequency synthesis using a Delay Locked Loop (DLL) are provided. The apparatus includes the DLL, an edge pulse generator, and an inductive-capacitive (LC) tank switch....
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US20090168552 |
Semiconductor memory device and method for operating the same
A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of...
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US20090167388 |
DELAY LOCKED LOOP CIRCUIT AND CONTROL METHOD OF THE SAME
A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying...
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US20090167387 |
DELAY-LOCKED LOOP FOR TIMING CONTROL AND DELAY METHOD THEREOF
A delay-locked loop for timing control, includes a voltage-controlled delay line that delays a reference clock to generate a multi-phase clock comprising a plurality of delayed phase clocks; and an...
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US20090160512 |
Delay control circuit and delay control method
A delay control circuit in which steady phase error can be eliminated has a first variable delay circuit and a first phase control circuit. The delay control circuit further includes a second...
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US20090153253 |
SYSTEM AND METHOD FOR REDUCING LOCK TIME IN A PHASE-LOCKED LOOP
Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very...
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US20090153205 |
METHODS, DEVICES, AND SYSTEMS FOR A DELAY LOCKED LOOP HAVING A FREQUENCY DIVIDED FEEDBACK CLOCK
Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal and output a delayed clock signal....
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US20090146710 |
Signal generating circuit
A signal generating circuit includes an input stage delay circuit which can switch a state of outputting a reference clock and a state of outputting a signal delaying the reference clock by a first...
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US20090146709 |
DELAY CIRCUIT OF DELAY LOCKED LOOP HAVING SINGLE AND DUAL DELAY LINES AND CONTROL METHOD OF THE SAME
A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first...
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US20090146708 |
DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME
A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of...
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