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US20120223740 |
RESET/LOAD AND SIGNAL DISTRIBUTION NETWORK
A tree-like signal distribution network comprises a plurality of branches extending from a plurality of branching points. The distribution network comprises a plurality of control blocks, each...
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US20100301903 |
BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY
A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is...
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US20110037498 |
VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI...
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US20120126848 |
MULTI-CHIP STACKED SYSTEM AND CHIP SELECT APPARATUS THEREOF
A multi-chip stacked system and a chip select apparatus are provided. The chip select apparatus includes n ID code generators and n activation logic units. The first ID code generator generates a...
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US20120293198 |
ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN
A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first...
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US20120133390 |
ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction....
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US20110032000 |
ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction....
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US20100315124 |
LOW POWER RECEIVER CIRCUIT
Subject matter disclosed herein relates to circuit design, and more particularly relates to low power circuit techniques for receiver circuits.
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US20120105099 |
Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design
Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the...
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US20120217991 |
IMPEDANCE CONTROL CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME
A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code...
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US20120112791 |
ROBUST TIME BORROWING PULSE LATCHES
Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock...
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US20110089974 |
ROBUST TIME BORROWING PULSE LATCHES
Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock...
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US20100327909 |
Keeper circuit
Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for...
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US20130106461 |
IMPLEMENTING SCREENING FOR SINGLE FET COMPARE OF PHYSICALLY UNCLONABLE FUNCTION (PUF)
A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect...
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US20120146684 |
SWITCH TO PERFORM NON-DESTRUCTIVE AND SECURE DISABLEMENT OF IC FUNCTIONALITY UTILIZING MEMS AND METHOD THEREOF
Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement...
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US20120068734 |
Integrated Circuit Leakage Power Reduction using Enhanced Gated-Q Scan Techniques
Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state....
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US20130120024 |
WAVE DYNAMIC DIFFERENTIAL LOGIC
Wave Dynamic Differential Logic (WDDL) is provided, wherein a differential logic stage is pre-charged or pre-discharged by a previous logic stage, such as, for example, a previous SDDL stage, a...
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US20130043898 |
SYSTEM WITH A DEFECT TOLERANT CONFIGURABLE IC
Some embodiments of the invention provide a system that includes a first defect tolerant configurable integrated circuit and a second IC communicatively coupled to the defect tolerant configurable...
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US20100308861 |
TERMINATION CIRCUIT AND IMPEDANCE MATCHING DEVICE INCLUDING THE SAME
An impedance matching device includes a calibration circuit configured to generate impedance calibration codes for modification of impedance; a code modification unit configured to modify the...
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US20110304352 |
Control Board For Connection Between FPGA Boards And Test Device Thereof
A Field Programmable Gate Arrays (FPGA) connection control board is provided. The FPGA connection control board includes a printed circuit board (PCB), a plurality of first connection terminals...
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US20110128038 |
IMPEDANCE ADJUSTING DEVICE
An impedance adjusting device includes: a calibration node; a comparison unit configured to compare a reference voltage with a voltage of the calibration node; a counting unit configured to...
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US20120274352 |
SINGLE EVENT TRANSIENT DIRECT MEASUREMENT METHODOLOGY AND CIRCUIT
A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells,...
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US20120119780 |
SINGLE EVENT TRANSIENT DIRECT MEASUREMENT METHODOLOGY AND CIRCUIT
A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells,...
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US20110291697 |
DIGITAL LOGIC CIRCUIT AND MANUFACTURE METHOD THEREOF
A digital logic circuit and a manufacture method of the digital logic circuit thereof are provided. The digital logic circuit includes a voltage rail, a ground rail, and a plurality of logic...
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US20120092039 |
IMPEDANCE CODE GENERATION CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME
An impedance code generation circuit includes an impedance unit configured to drive a calibration node to a first level by using an impedance value determined by an impedance code, a code...
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US20120112792 |
ONE PHASE LOGIC
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are...
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US20110298495 |
ONE PHASE LOGIC
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are...
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US20120223741 |
POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICATIONS
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data...
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US20120242370 |
INVERTER, NAND GATE, AND NOR GATE
Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal...
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US20120098564 |
Reversing the Weak Measurement on a Qubit
Methods and systems are disclosed for restoring a state of a qubit transformed by a weak measurement to its original state. Unlike traditional methods, in which, the restoration was carried out by...
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US20120256654 |
REAL TIME AVERAGED IMPEDANCE CALIBRATION FOR ON-DIE TERMINATION
An averaged impedance calibration is obtained by utilizing two separately controlled resistive loads arranged in parallel and choosing two adjacent control codes to configure switch arrays to set...
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US20070008011 |
Distributed power and clock management in a computerized system
A computer circuit includes a plurality of digital logic circuits, each having a locally regulated voltage supply and a clock. The clock and locally regulated voltage supply of each of the...
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US20060273826 |
Heat dissipation system
A heat dissipation system includes at least one fan, at least two controllers, a signal generator, and a signal converter. The controllers are electrically connected to the fan and generate an...
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US20130049797 |
IMPEDANCE CALIBRATION CIRCUIT AND METHOD
An embodiment of an impedance calibration circuit and method, a device including an impedance calibration circuit, and a transmission link system.
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US20110140733 |
Dynamic Voltage and Frequency Management
In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes...
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US20130009665 |
Integrated Circuit Elementary Cell with a Low Sensitivity to External Disturbances
The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external...
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US20100327902 |
Power saving termination circuits for dram modules
The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes...
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US20120306537 |
ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT
A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a...
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US20120032704 |
INTEGRATION OF OPEN SPACE/DUMMY METAL AT CAD FOR PHYSICAL DEBUG OF NEW SILICON
An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is...
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US20130069692 |
STATE TRANSITIONING CLOCK GATING
In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements,...
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US20110271128 |
STATE TRANSITIONING CLOCK GATING
In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements,...
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US20110121862 |
CIRCUIT WITH STACKED STRUCTURE AND USE THEREOF
An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a...
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US20120176155 |
RESCALING
A novel method for designing an integrated circuit (“IC”) by resealing an original set of circuits in a design of the IC is disclosed. The original set of circuits to be resealed includes seq...
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US20120133392 |
MULTIPLEX GATE DRIVING CIRCUIT
A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the...
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US20130088261 |
LOW LEAKAGE SPARE GATES FOR INTEGRATED CIRCUITS
Devices, systems, methods, and other embodiments associated with spare gates are described. In one embodiment, a spare gate in an integrated circuit has a disconnected discharge path to minimize or...
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US20080054933 |
SCAN CHAIN IN A CUSTOM ELECTRONIC CIRCUIT DESIGN
The present invention relates to a scan chain and related cell design structures in a custom electronic circuit design with a plurality of storage elements. All scan inputs and all scan outputs of...
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US20110133781 |
LOW POWER COMPLEMENTARY LOGIC LATCH AND RF DIVIDER
A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch...
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US20120242371 |
POWER EFFICIENT MULTIPLEXER
A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input...
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US20100013517 |
RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics (302, 304) for integrated circuits and methods for designing asynchronous circuits to be...
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US20070262791 |
Integrated Circuit to Store a Datum
An integrated circuit includes a programmable circuit with a programmable element, and a storage circuit to store a storage state depending on a programming state of the programmable element of the...
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