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US20120223740 RESET/LOAD AND SIGNAL DISTRIBUTION NETWORK  
A tree-like signal distribution network comprises a plurality of branches extending from a plurality of branching points. The distribution network comprises a plurality of control blocks, each...
US20100301903 BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY  
A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is...
US20140292374 METHOD FOR CONTROLLING AN INTEGRATED CIRCUIT  
A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and...
US20110037498 VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS  
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI...
US20120126848 MULTI-CHIP STACKED SYSTEM AND CHIP SELECT APPARATUS THEREOF  
A multi-chip stacked system and a chip select apparatus are provided. The chip select apparatus includes n ID code generators and n activation logic units. The first ID code generator generates a...
US20130241597 INTEGRATED CIRCUIT WITH TIMING AWARE CLOCK-TREE AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT  
An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock...
US20120293198 ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN  
A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first...
US20120133390 ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN  
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction....
US20110032000 ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN  
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction....
US20100315124 LOW POWER RECEIVER CIRCUIT  
Subject matter disclosed herein relates to circuit design, and more particularly relates to low power circuit techniques for receiver circuits.
US20130293259 HOMOGENEOUS DUAL-RAIL LOGIC FOR DPA ATTACK RESISTIVE SECURE CIRCUIT DESIGN  
Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the...
US20120105099 Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design  
Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the...
US20120217991 IMPEDANCE CONTROL CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME  
A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code...
US20140292367 Protecting Quantum Entanglement from Amplitude Damping in a Two Qubit System  
Preservation of quantum entanglement in a two-qubit system is achieved by use of the disclosed systems. Three different example two-qubit systems are shown: (1) a system employing a weak...
US20140285236 FLIP-FLOP CIRCUIT WITH RESISTIVE POLY ROUTING  
A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state...
US20140097870 NANO-ELECTRO-MECHANICAL-SWITCH ADIABATIC DYNAMIC LOGIC CIRCUITS  
A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising...
US20140062532 NANO-ELECTRO-MECHANICAL-SWITCH ADIABATIC DYNAMIC LOGIC CIRCUITS  
A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising...
US20120112791 ROBUST TIME BORROWING PULSE LATCHES  
Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock...
US20110089974 ROBUST TIME BORROWING PULSE LATCHES  
Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock...
US20130307580 MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTURES THEREOF  
Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided....
US20130234754 MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTURES THEREOF  
Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided....
US20140015501 CIRCUIT FOR DRIVING GATE OF POWER MOS TRANSISTOR  
A circuit for driving a gate of a power MOS transistor includes an adaptive pull-up unit and an adaptive pull-down unit. The adaptive pull-up unit is connected between a first power source voltage...
US20140097868 FINE GRAIN PROGRAMMABLE GATE ARCHITECTURE WITH HYBRID LOGIC/ROUTING ELEMENT AND DIRECT-DRIVE ROUTING  
An apparatus is disclosed herein for a programmable gate architecture with hybrid logic/routing circuitry. In one embodiment, a programmable gate array comprises a plurality of hybrid logic or...
US20100327909 Keeper circuit  
Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for...
US20130106461 IMPLEMENTING SCREENING FOR SINGLE FET COMPARE OF PHYSICALLY UNCLONABLE FUNCTION (PUF)  
A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect...
US20120146684 SWITCH TO PERFORM NON-DESTRUCTIVE AND SECURE DISABLEMENT OF IC FUNCTIONALITY UTILIZING MEMS AND METHOD THEREOF  
Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement...
US20140197864 Non-Volatile Latch Structures with Small Area for FPGA  
A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second...
US20140320169 CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY  
A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to...
US20130241593 INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES  
Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state....
US20120068734 Integrated Circuit Leakage Power Reduction using Enhanced Gated-Q Scan Techniques  
Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state....
US20130265080 SOFT ERROR RESILIENT FPGA  
A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER...
US20130181738 SOFT ERROR RESILIENT FPGA  
A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER...
US20130120024 WAVE DYNAMIC DIFFERENTIAL LOGIC  
Wave Dynamic Differential Logic (WDDL) is provided, wherein a differential logic stage is pre-charged or pre-discharged by a previous logic stage, such as, for example, a previous SDDL stage, a...
US20130043898 SYSTEM WITH A DEFECT TOLERANT CONFIGURABLE IC  
Some embodiments of the invention provide a system that includes a first defect tolerant configurable integrated circuit and a second IC communicatively coupled to the defect tolerant configurable...
US20140197863 PLACEMENT OF STORAGE CELLS ON AN INTEGRATED CIRCUIT  
A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the...
US20140070845 TRANSMITTER SWING CONTROL CIRCUIT AND METHOD  
Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.
US20100308861 TERMINATION CIRCUIT AND IMPEDANCE MATCHING DEVICE INCLUDING THE SAME  
An impedance matching device includes a calibration circuit configured to generate impedance calibration codes for modification of impedance; a code modification unit configured to modify the...
US20140292373 TERNARY T ARITHMETIC CIRCUIT  
A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS,...
US20110304352 Control Board For Connection Between FPGA Boards And Test Device Thereof  
A Field Programmable Gate Arrays (FPGA) connection control board is provided. The FPGA connection control board includes a printed circuit board (PCB), a plurality of first connection terminals...
US20130214812 IMPEDANCE TUNING CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME  
An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration...
US20140167813 DIGITAL CLAMP FOR STATE RETENTION  
Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is...
US20110128038 IMPEDANCE ADJUSTING DEVICE  
An impedance adjusting device includes: a calibration node; a comparison unit configured to compare a reference voltage with a voltage of the calibration node; a counting unit configured to...
US20120274352 SINGLE EVENT TRANSIENT DIRECT MEASUREMENT METHODOLOGY AND CIRCUIT  
A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells,...
US20120119780 SINGLE EVENT TRANSIENT DIRECT MEASUREMENT METHODOLOGY AND CIRCUIT  
A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells,...
US20140203839 Dynamic Adaptation of Continuous Time Linear Equalization Circuits  
An embodiment of the invention includes dynamically adjusting gain peaking of circuit logic such that error rates are acceptable across various process/voltage/temperature (PVT) ranges. An...
US20110291697 DIGITAL LOGIC CIRCUIT AND MANUFACTURE METHOD THEREOF  
A digital logic circuit and a manufacture method of the digital logic circuit thereof are provided. The digital logic circuit includes a voltage rail, a ground rail, and a plurality of logic...
US20120092039 IMPEDANCE CODE GENERATION CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME  
An impedance code generation circuit includes an impedance unit configured to drive a calibration node to a first level by using an impedance value determined by an impedance code, a code...
US20140184271 LOW CLOCK-POWER INTEGRATED CLOCK GATING CELL  
In an integrated clock gating (ICG) cell a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to generate a latch output in response to the state of the...
US20120112792 ONE PHASE LOGIC  
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are...
US20110298495 ONE PHASE LOGIC  
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are...