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US20060255836 |
Clock driver circuit and driving method therefor
A clock driver circuit has a plurality of driver circuits 20, 30 connected in parallel with each other, and a control circuit 40 for stopping the operation of a part of the plurality of driver...
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US20090309631 |
CIRCUIT WITH ENHANCED MODE AND NORMAL MODE
Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another...
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US20100085078 |
Digital Logic Voltage Level Shifter
A digital logic level shifter having three stages. An initial stage includes a conventional 4-terminal bridge-type inverter circuit. A middle stage includes a 5-terminal first logic reversing...
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US20080126468 |
Decoding apparatus for vector booth multiplication
A decoding apparatus for Booth multiplication includes a NAND gate, a first and a second OR gate coupled to the NAND gate, a first and a second exclusive NOR gate coupled respectively to the OR...
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US20120105102 |
MAGNETIC LOGIC GATE
This disclosure is directed to a magnetic logic device for implementing a combinational logic function. The magnetic logic device may include a chain of at least two magnetoresistive devices...
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US20060232298 |
Signal issuing unit
A signal issuing unit for issuance of at least one electrical output signal. The signal issuing unit includes: At least one contact unit, which is embodied in such a manner that a digital...
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US20120194220 |
Frequency Divider with Synchronous Range Extension Across Octave Boundaries
A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and...
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US20090027081 |
Eight Transistor Tri-State Driver Implementing Cascade Structures To Reduce Peak Current Consumption, Layout Area and Slew Rate
An eight-transistor tri-state driver. The tri-state driver implements multiple cascade structures where each cascade structure may refer to a pair of complementary transistors serially connected....
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US20090237113 |
SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM TRANSFORMATION APPARATUS, AND MAPPING APPARATUS
A semiconductor integrated circuit (100) according to the present invention includes a plurality of reconfigurable cores (101) arranged separately from each other in a matrix, and a first group of...
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US20130007086 |
METHOD OF OPTIMIZING COMBINATIONAL CIRCUITS
A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a...
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US20090128188 |
Pad invariant FPGA and ASIC devices
A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having...
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US20100308859 |
Local Interconnect Network Transceiver Driver
Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input...
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US20130093465 |
ASYMMETRICAL BUS KEEPER
Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first...
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US20050163247 |
Isolation barrier for interfacing a line side device to a system side device
According to one embodiment, an isolation barrier comprises a transformer and a controlled impedance module. The system side device generates an amplitude modulated clock signal when the system...
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US20070182455 |
AND type match circuit structure for content-addressable memories
This invention provides An AND type match circuit structure for content-addressable memories adopting the Pseudo-Footless Clock-and-Data Pre-charged Dynamic circuit as an AND type match circuit...
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US20090267643 |
FLEXIBLE ADDER CIRCUITS WITH FAST CARRY CHAIN CIRCUITRY
Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a...
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US20100060309 |
MULTI-ROW BLOCK SUPPORTING ROW LEVEL REDUNDANCY IN A PLD
In a Programmable Logic Device (PLD), a multi-row block that has internal logic connections between rows has redundant internal connections between rows to replace the internal logic connections...
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US20120126849 |
TERMINATION CIRCUIT FOR ON-DIE TERMINATION
In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit...
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US20090219054 |
CURRENT MODE LOGIC DIGITAL CIRCUITS
A digital circuit comprises: a first arm including a first metal oxide semiconductor field effect transistor (M3) configured to act as a load device; a second arm including a second metal oxide...
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US20070247182 |
Protection of security key information
A protection circuit is disclosed, for preventing access to stored security key data after the security key is no longer used. The protection circuit performs operations on a programming circuit...
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US20120062274 |
SCHMITT CIRCUIT
The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit...
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US20090115447 |
Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit
A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state...
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US20130009664 |
(N-1)-OUT-OF-N VOTER MUX WITH ENHANCED DRIVE
This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the...
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US20120126853 |
LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN
A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for...
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US20050083082 |
Retention device for a dynamic logic stage
A retention device stabilizes the logic output levels of a dynamic logic stage. The dynamic logic stage contains an inverter, which generates an inverted logic signal that is used as a feedback...
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US20090267640 |
SYSTEM INCLUDING PREEMPHASIS DRIVER CIRCUIT AND METHOD
A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary...
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US20100001761 |
Multi-function input terminal of integrated circuits
A single terminal is used to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is...
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US20060125526 |
Differential analog logic circuit with symmetric inputs and output
A logic circuit incorporates symmetric inputs and/or a symmetric output. The logic circuit may include symmetric input circuits such that each input signal may be processed by a circuit that...
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US20090206879 |
Signal transmission circuit and signal transmission system using the same
A signal transmission circuit includes first and second power source wirings, and a plurality of differential circuits connected in series between the first and second power source wirings. A...
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US20090102507 |
DESIGN STRUCTURE FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING
A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a...
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US20120200313 |
APPARATUS FOR CLOCKED POWER LOGIC AGAINST POWER ANALYSIS ATTACK
A logic apparatus secure against a power analysis attack is disclosed. The logic apparatus may include a clocked power logic to recover and reuse at least a part of charges supplied during a single...
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US20120043991 |
Scan Cell Use With Reduced Power Consumption
Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively...
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US20090080260 |
Programmable CSONOS logic element
A complementary SONOS-type (CSONOS) logic device is programmed and erased with a common voltage. The CSONOS device retains data integrity over extended read endurance cycles.
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US20060066350 |
Equalizing driver circuit and method of operating same
An equalizing driver circuit is disclosed. In one particular exemplary embodiment, the equalizing driver circuit may comprise dedicated driver circuitry having a first current source switchably...
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US20120074983 |
Integrated Circuit with Configurable On-Die Termination
Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination...
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US20110128041 |
Integrated Circuit With Configurable On-Die Termination
Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination...
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US20130043906 |
CMOS LOGIC CIRCUIT
A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS...
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US20080175045 |
DEPLETION-MODE MOSFET CIRCUIT AND APPLICATIONS
Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and...
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US20100188115 |
Dynamic Voltage and Frequency Management
In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes...
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US20070013411 |
Apparatus and methods for programmable slew rate control in transmitter circuits
High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate...
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US20100090720 |
FLEXIBLE PARALLEL/SERIAL RECONFIGURABLE ARRAY CONFIGURATION SCHEME
A programming interface device for a programmable logic circuit, the programmable logic circuit comprising a series of parallel logic block chains each having first and second connection means, the...
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US20110133778 |
NON-VOLATILE LOGIC CIRCUITS, INTEGRATED CIRCUITS INCLUDING THE NON-VOLATILE LOGIC CIRCUITS, AND METHODS OF OPERATING THE INTEGRATED CIRCUITS
Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to...
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US20090160479 |
Transceiver Having an Adjustable Terminating Network for a Control Device
In a transceiver for a control unit having a transceiver core for adapting the level of messages received or to be sent, an adjustable terminating network is situated in the transceiver that makes...
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US20080258759 |
UNIVERSAL DIGITAL BLOCK INTERCONNECTION AND CHANNEL ROUTING
A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs...
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US20090121740 |
Audio/Video Router
Technique for Routing digital audio and digital video signals commences by routing a digital video signal, devoid of embedded digital audio, to at least one output, typically by way of a video...
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US20090267649 |
Clock Gating System and Method
A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an...
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US20110025374 |
Multi-Drop Bus System
A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each...
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US20080204075 |
INTERFACING OF CIRCUITS IN AN INTEGRATED ELECTRONIC CIRCUIT
An interface having internal conductors to transfer data between a sending circuit and a receiving circuit in an integrated electronic circuit, the receiving circuit including an input buffer...
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US20110169525 |
SYSTEMS, PIPELINE STAGES, AND COMPUTER READABLE MEDIA FOR ADVANCED ASYNCHRONOUS PIPELINE CIRCUITS
Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable...
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US20110043249 |
High Voltage Tolerant Input/Output Interface Circuit
An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an...
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