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US20110133779 INTERFACE CIRCUIT  
An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a...
US20110133775 INTERFACE CIRCUIT  
An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a...
US20140055164 BUFFER SYSTEM HAVING REDUCED THRESHOLD CURRENT  
A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management...
US20090309628 SEMICONDUCTOR MEMORY DEVICE AND ON-DIE TERMINATION CIRCUIT  
An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each...
US20090140772 ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES  
Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging...
US20090271135 Detecting Device for Detecting an Operating Mode of a System and Detecting Method Thereof  
A detecting device for detecting an operating mode is disclosed. The detecting device includes a pulse generator and a hold-up unit. The pulse generator is disposed for issuing a one-shot pulse...
US20110199121 SMART EDGE DETECTOR  
In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D2) to trigger a first flip-flop having a first clock in a...
US20110240737 ELECTRONIC DEVICE AND PROTECTION MECHANISM THEREOF  
An electronic device includes a protection mechanism, a first circuit board having a first electronic loop, and a second circuit board having a second electronic loop. The protection mechanism is...
US20090309627 Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits  
The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention,...
US20130115907 VARIABLE DUTY-CYCLE MULTI-STANDARD MIXER  
An adjustable mixer is disclosed that is capable of operating in different modes in order to satisfy the mixing requirement of multiple radio access technologies (RATs). The adjustable mixer...
US20120262200 HIGH DEFINITION MULTIMEDIA INTERFACE (HDMI) APPARATUS INCLUDING TERMINATION CIRCUIT  
A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias...
US20130093462 CONFIGURABLE STORAGE ELEMENTS  
A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that...
US20100060311 CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES  
An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks...
US20100176840 SUPERCONDUCTIVE CROSSBAR SWITCH  
A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with...
US20100148818 HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT  
A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage...
US20120112786 MICRO-GRANULAR DELAY TESTING OF CONFIGURABLE ICS  
A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method...
US20110068820 Micro-Granular Delay Testing of Configurable ICs  
A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method...
US20140306736 STATE MACHINE CIRCUIT AND STATE ADJUSTING METHOD  
A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value,...
US20080231317 Staggered logic array block architecture  
A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of...
US20140285232 Methods and Systems for Reducing Supply and Termination Noise  
Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the...
US20120182044 Methods and Systems for Reducing Supply and Termination Noise  
Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the...
US20080288906 Integrated system on module  
An electronic product includes a circuit board, an integrated system on module, and an application-specific module. The integrated system on module and the application-specific module are...
US20080222592 SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD  
A semiconductor integrated circuit including a user logic circuit is disclosed in which circuit parts for shifting data are composed of registers other than scan cells except for the circuit part...
US20070103185 Dual path redundancy with stacked transistor voting  
A method of operation and an apparatus for radiation hardening a combinational logic circuit are presented. A section of logic that is to be radiation hardened is identified. An entire logic...
US20140232430 METHODS AND SYSTEMS TO STRESS-PROGRAM AN INTEGRATED CIRCUIT  
Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program,...
US20120286822 AUTOMATED METAL PATTERN GENERATION FOR INTEGRATED CIRUCITS  
An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the...
US20070176640 Dynamic circuit  
The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a...
US20090134912 ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS  
A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an...
US20070176641 Low swing domino logic circuits  
Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper...
US20130278287 Low Leakage Boundary Scan Device Design and Implementation  
A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving...
US20080169842 DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT  
A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated...
US20090251172 SINGLE ELECTRON BASED FLEXIBLE MULTI-FUNCTIONAL LOGIC CIRCUIT AND THE TRANSISTOR THEREOF  
The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs)...
US20140210510 BYPASSABLE CLOCKED STORAGE CIRCUITRY FOR DYNAMIC VOLTAGE-FREQUENCY SCALING  
Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input...
US20110050281 METHOD AND SYSTEM FOR GROUPING LOGIC IN AN INTEGRATED CIRCUIT DESIGN TO MINIMIZE NUMBER OF TRANSISTORS AND NUMBER OF UNIQUE GEOMETRY PATTERNS  
A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors,...
US20070146008 Semiconductor circuit comprising vertical transistor  
A semiconductor circuit comprising a vertical transistor is disclosed. A differential amplifier circuit comprises a pair of amplification transistors, wherein the pair of amplification transistors...
US20090108872 INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION  
An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two...
US20120081150 Method of adapting standard cells  
A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell...
US20070194805 Data output driving circuit of semiconductor memory apparatus  
A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a...
US20080218209 Device for Controlling Terminal State, Method Thereof, and Device for Transmitting Paging Message  
The present invention relates to a device for controlling a state of a terminal with respect to mobility management, and a method thereof. The state of the terminal includes a disconnected state...
US20100271068 LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA  
A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the...
US20110084723 Built-in Line Test Method  
A method for testing a line including an input/output pin of a programmable logic circuit, said line including at least one individual line extending from the input/output pin to a peripheral...
US20090273363 OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE  
Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up...
US20100026338 Fault triggerred automatic redundancy scrubber  
A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is...
US20070103195 High speed and low power SRAM macro architecture and method  
Circuits and methods are described for reducing leakage power in integrated circuit devices whose logic transistors (e.g., logic circuits, latches, and/or output stages) are powered through one or...
US20090134910 RECONFIGURABLE LOGIC STRUCTURES  
Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a...
US20130113514 SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL  
A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is...
US20100026343 CLOCKED SINGLE POWER SUPPLY LEVEL SHIFTER  
First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that...
US20120062277 Reconfigurable Logic Automata  
A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A...
US20110001513 CMOS INPUT BUFFER CIRCUIT  
Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes:...
US20090243656 OUTPUT BUFFER FOR AN ELECTRONIC DEVICE  
In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first...