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US20130113514 SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL  
A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is...
US20100026343 CLOCKED SINGLE POWER SUPPLY LEVEL SHIFTER  
First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that...
US20120062277 Reconfigurable Logic Automata  
A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A...
US20110001513 CMOS INPUT BUFFER CIRCUIT  
Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes:...
US20090243656 OUTPUT BUFFER FOR AN ELECTRONIC DEVICE  
In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first...
US20060125514 Semiconductor integrated circuit having interface circuit containing pull-up resistor and blocking diode, circuit module including such integrated circuit, and electronic apparatus including such circuit modules  
In a semiconductor integrated circuit having an interface circuit adapted to be connected to a power supply line connected to the interface circuit, and a signal line connected to the interface...
US20080231329 DIFFERENTIAL SIGNAL OUTPUT CIRCUIT FOR TIMING CONTROLLER OF DISPLAY DEVICE  
A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for...
US20100171525 HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS  
A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be...
US20130093458 BINARY HALF-ADDER USING OSCILLATORS  
A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator,...
US20130027085 ADJUSTABLE SCHMITT TRIGGER  
A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first...
US20080238473 Push-Pull Pulse Register Circuit  
A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having...
US20080098342 Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device  
A simple method for designing a semiconductor integrated circuit having the ZSCCMOS structure is provided. For each kind of primitive logic gate, a logic gate cell H and a layout cell H each having...
US20090085603 FPGA configuration protection and control using hardware watchdog timer  
An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that...
US20090009212 Calibration system and method  
A system and method to calibrate an output driver impedance of an output driver based on a termination device of a controller.
US20140002130 IMPEDANCE CALIBRATION CIRCUITS  
An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first...
US20130285699 RE-PROGRAMMABLE ANTIFUSE FPGA UTILIZING RESISTIVE CeRAM ELEMENTS  
A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, the FPGA comprising: a plurality of CeRAM resistive switching elements forming a connection block, the switching...
US20100117683 HARDWARE SYNTHESIS FROM MULTICYCLE RULES  
Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides...
US20100328984 PIEZO-EFFECT TRANSISTOR DEVICE AND APPLICATIONS  
A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode...
US20130038366 BIST CIRCUIT FOR PHASE MEASUREMENT  
A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference...
US20060119392 Semiconductor integrated circuit and layout design method thereof, and standard cell  
A semiconductor integrated circuit comprises: a first standard cell which includes a first logic circuit and a first switch for controlling current supply to the first logic circuit; and a second...
US20110062983 REDUCING SWITCHING NOISE  
Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a...
US20120236378 METHOD AND APPARATUS FOR SIMULTANEOUS PROCESSING OF MULTIPLE FUNCTIONS  
Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At...
US20100237903 Configurable On-Die Termination  
Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail...
US20090167346 RECONFIGURABLE CIRCUIT, CONFIGURATION METHOD AND PROGRAM  
The present invention is intended to provide a reconfigurable circuit, a configuration method and a program capable of significantly shortening the configuration time without increasing the area of...
US20090160480 Termination circuit  
In order to prevent malfunction due to fluctuations in signal level, a terminating resistor circuit includes terminating resistors the connections whereof to an input/output terminal are capable of...
US20070159210 Operation mode setting circuit, LSI having operation mode setting circuit, and operation mode setting method  
According to one embodiment, a logical circuit performs an AND operation based on a mode signal input via a mode terminal and a signal formed by delaying a system reset signal as much as one clock...
US20080191735 Accessing multiple user states concurrently in a configurable IC  
Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes...
US20070214437 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS CIRCUIT INSERTING METHOD  
A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable...
US20050110525 Current-mode logic circuit  
A current-mode logic (CML) circuit includes: a first field effect transistor (FET) operable based on a digital signal; a second FET operable based on an inverted digital signal; a first load...
US20130162295 CLOCK GENERATOR INTERMITTENTLY GENERATING SYNCHRONOUS CLOCK  
A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data...
US20110291699 IMPEDANCE CODE GENERATION CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR SETTING TERMINATION IMPEDANCE  
An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code...
US20140125377 DUAL FLIP-FLOP CIRCUIT  
A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The...
US20070182456 Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form  
An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form...
US20110006810 LOW-SWING CMOS INPUT CIRCUIT  
The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art. The CMOS input circuit according...
US20130314123 LOOKUP TABLE AND PROGRAMMABLE LOGIC DEVICE INCLUDING LOOKUP TABLE  
A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of...
US20100079166 Programmable Signal Routing Systems Having Low Static Leakage  
Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where...
US20090033363 Multi-function input terminal  
A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1)...
US20090009434 High power address driver and display device employing the same  
An address driver includes an energy recovery circuit and an output stage connected to the energy recovery circuit. The output stage is connected to the energy recovery circuit and is formed of a...
US20080218202 Reconfigurable array to compute digital algorithms  
An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is described.
US20080197876 INTEGRATED CIRCUIT, SYSTEM AND METHOD INCLUDING A PERFORMANCE TEST MODE  
An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N...
US20130278285 MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA  
PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors...
US20110062991 ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASYNCHRONOUS INPUTS  
A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a...
US20100019798 SPIN MOSFET AND RECONFIGURABLE LOGIC CIRCUIT USING THE SPIN MOSFET  
It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has...
US20080129330 Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit  
An integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry...
US20070247195 LOW OUTPUT-TO-OUTPUT SKEW/LOW JITTER STAGGERED OUTPUT BUFFER  
A system and method for generating multiple current steered output signals at a centralized location and subsequently routing them to their respective output pads is shown and described. The system...
US20140176188 HETEROGENEOUS HIGH-SPEED SERIAL INTERFACE SYSTEM ARCHITECTURE  
One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical...
US20090167357 EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS  
An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding...
US20080278198 Buffer for Object Information  
A buffer that is state-aware and/or node-oriented. In a state-aware buffer, one or more operations relating to a state can be performed. In a node-oriented buffer, instances of a node can be...
US20080048725 Domino Circuit with Master and Slave (DUAL) Pull Down Paths  
A domino circuit and method include a master evaluation node to which a master discharge path with a wide input AND gate is coupled and a virtual evaluation node to which an output stage and slave...
US20070247196 Circuit and method for configuring a circuit  
A circuit and method for configuring a circuit is disclosed. In one embodiment, the circuit includes at least one pull-down path, wherein an amount of a current flowing through the pull-down path...