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US20070176641 Low swing domino logic circuits  
Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper...
US20130278287 Low Leakage Boundary Scan Device Design and Implementation  
A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving...
US20080169842 DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT  
A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated...
US20090251172 SINGLE ELECTRON BASED FLEXIBLE MULTI-FUNCTIONAL LOGIC CIRCUIT AND THE TRANSISTOR THEREOF  
The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs)...
US20140210510 BYPASSABLE CLOCKED STORAGE CIRCUITRY FOR DYNAMIC VOLTAGE-FREQUENCY SCALING  
Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input...
US20110050281 METHOD AND SYSTEM FOR GROUPING LOGIC IN AN INTEGRATED CIRCUIT DESIGN TO MINIMIZE NUMBER OF TRANSISTORS AND NUMBER OF UNIQUE GEOMETRY PATTERNS  
A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors,...
US20070146008 Semiconductor circuit comprising vertical transistor  
A semiconductor circuit comprising a vertical transistor is disclosed. A differential amplifier circuit comprises a pair of amplification transistors, wherein the pair of amplification transistors...
US20090108872 INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION  
An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two...
US20120081150 Method of adapting standard cells  
A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell...
US20070194805 Data output driving circuit of semiconductor memory apparatus  
A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a...
US20080218209 Device for Controlling Terminal State, Method Thereof, and Device for Transmitting Paging Message  
The present invention relates to a device for controlling a state of a terminal with respect to mobility management, and a method thereof. The state of the terminal includes a disconnected state...
US20100271068 LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA  
A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the...
US20110084723 Built-in Line Test Method  
A method for testing a line including an input/output pin of a programmable logic circuit, said line including at least one individual line extending from the input/output pin to a peripheral...
US20090273363 OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE  
Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up...
US20100026338 Fault triggerred automatic redundancy scrubber  
A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is...
US20070103195 High speed and low power SRAM macro architecture and method  
Circuits and methods are described for reducing leakage power in integrated circuit devices whose logic transistors (e.g., logic circuits, latches, and/or output stages) are powered through one or...
US20090134910 RECONFIGURABLE LOGIC STRUCTURES  
Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a...
US20130113514 SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL  
A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is...
US20100026343 CLOCKED SINGLE POWER SUPPLY LEVEL SHIFTER  
First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that...
US20120062277 Reconfigurable Logic Automata  
A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A...
US20110001513 CMOS INPUT BUFFER CIRCUIT  
Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes:...
US20090243656 OUTPUT BUFFER FOR AN ELECTRONIC DEVICE  
In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first...
US20060125514 Semiconductor integrated circuit having interface circuit containing pull-up resistor and blocking diode, circuit module including such integrated circuit, and electronic apparatus including such circuit modules  
In a semiconductor integrated circuit having an interface circuit adapted to be connected to a power supply line connected to the interface circuit, and a signal line connected to the interface...
US20080231329 DIFFERENTIAL SIGNAL OUTPUT CIRCUIT FOR TIMING CONTROLLER OF DISPLAY DEVICE  
A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for...
US20100171525 HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS  
A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be...
US20130093458 BINARY HALF-ADDER USING OSCILLATORS  
A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator,...
US20130027085 ADJUSTABLE SCHMITT TRIGGER  
A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first...
US20080238473 Push-Pull Pulse Register Circuit  
A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having...
US20080098342 Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device  
A simple method for designing a semiconductor integrated circuit having the ZSCCMOS structure is provided. For each kind of primitive logic gate, a logic gate cell H and a layout cell H each having...
US20090085603 FPGA configuration protection and control using hardware watchdog timer  
An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that...
US20090009212 Calibration system and method  
A system and method to calibrate an output driver impedance of an output driver based on a termination device of a controller.
US20140002130 IMPEDANCE CALIBRATION CIRCUITS  
An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first...
US20130285699 RE-PROGRAMMABLE ANTIFUSE FPGA UTILIZING RESISTIVE CeRAM ELEMENTS  
A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, the FPGA comprising: a plurality of CeRAM resistive switching elements forming a connection block, the switching...
US20100117683 HARDWARE SYNTHESIS FROM MULTICYCLE RULES  
Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides...
US20100328984 PIEZO-EFFECT TRANSISTOR DEVICE AND APPLICATIONS  
A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode...
US20130038366 BIST CIRCUIT FOR PHASE MEASUREMENT  
A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference...
US20060119392 Semiconductor integrated circuit and layout design method thereof, and standard cell  
A semiconductor integrated circuit comprises: a first standard cell which includes a first logic circuit and a first switch for controlling current supply to the first logic circuit; and a second...
US20110062983 REDUCING SWITCHING NOISE  
Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a...
US20120236378 METHOD AND APPARATUS FOR SIMULTANEOUS PROCESSING OF MULTIPLE FUNCTIONS  
Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At...
US20100237903 Configurable On-Die Termination  
Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail...
US20090167346 RECONFIGURABLE CIRCUIT, CONFIGURATION METHOD AND PROGRAM  
The present invention is intended to provide a reconfigurable circuit, a configuration method and a program capable of significantly shortening the configuration time without increasing the area of...
US20090160480 Termination circuit  
In order to prevent malfunction due to fluctuations in signal level, a terminating resistor circuit includes terminating resistors the connections whereof to an input/output terminal are capable of...
US20070159210 Operation mode setting circuit, LSI having operation mode setting circuit, and operation mode setting method  
According to one embodiment, a logical circuit performs an AND operation based on a mode signal input via a mode terminal and a signal formed by delaying a system reset signal as much as one clock...
US20080191735 Accessing multiple user states concurrently in a configurable IC  
Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes...
US20070214437 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS CIRCUIT INSERTING METHOD  
A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable...
US20050110525 Current-mode logic circuit  
A current-mode logic (CML) circuit includes: a first field effect transistor (FET) operable based on a digital signal; a second FET operable based on an inverted digital signal; a first load...
US20130162295 CLOCK GENERATOR INTERMITTENTLY GENERATING SYNCHRONOUS CLOCK  
A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data...
US20110291699 IMPEDANCE CODE GENERATION CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR SETTING TERMINATION IMPEDANCE  
An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code...
US20140125377 DUAL FLIP-FLOP CIRCUIT  
A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The...
US20070182456 Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form  
An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form...