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US20090295432 CMOS BACK-GATED KEEPER TECHNIQUE  
A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail....
US20140232431 Clock Gater with Independently Programmable Delay  
An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising...
US20100301901 UNIVERSAL TWO-INPUT LOGIC GATE THAT IS CONFIGURABLE AND CONNECTABLE IN AN INTEGRATED CIRCUIT BY A SINGLE MASK LAYER ADJUSTMENT  
A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a...
US20100060310 Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects  
An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing...
US20090212818 Integrated circuit design method for improved testability  
An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a...
US20130176051 RECONFIGURABLE CIRCUIT  
A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring...
US20130002297 BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS  
A Bias Temperature Instability- (BTI-) resistance circuit is arranged to propagate a received clock signal through a clock tree. The state of the clock signal is inverted at a midpoint of the...
US20130002288 Electronic Circuit Arrangement for Processing Binary Input Values  
Electronic circuit arrangement for processing binary input values xεX of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input...
US20070146011 Duty cycle adjustment  
Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock...
US20090115449 ON DIE TERMINATION DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME  
On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration...
US20120049890 LOGIC CIRCUITS USING CARBON NANOTUBE TRANSISTORS  
In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.
US20090195268 Level Shifting Circuit and Method  
In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal...
US20120112793 Low-Current Logic-Gate Circuit  
A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and...
US20100058274 FLEXIBLE HARDWARE UPGRADE MECHANISM FOR DATA COMMUNICATIONS EQUIPMENT  
Partial reconfiguration of programmable logic devices may be achieved in a hardware-controlled manner without relying upon software. Upon installation of a new memory module, partial...
US20070024316 CIRCUIT PERSONALIZATION  
A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key,...
US20110199117 TRIGGER CIRCUITS AND EVENT COUNTERS FOR AN IC  
Some embodiments provide an integrated circuit (‘IC’). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also...
US20090027084 RAPID RESPONSE PUSH-UP PULL-DOWN BUFFER CIRCUIT  
A rapid response push-up pull-down buffer circuit configuration is used as an output buffer of a semiconductor memory device. The buffer circuit includes a pre-driver outputting a driving signal...
US20090121741 SEMICONDUCTOR APPARATUS, ON-DIE TERMINATION CIRCUIT, AND CONTROL METHOD OF THE SAME  
An on-die termination circuit of a semiconductor apparatus can include: a code converting unit configured to change a code value of a termination code in response to a termination control signal;...
US20110043245 COMPONENT PROVIDED WITH AN INTEGRATED CIRCUIT COMPRISING A CRYPTOROCESSOR AND METHOD OF INSTALLATION THEREOF  
In order to protect an integrated circuit provided with a cryptoprocessor from attacks aiming to reveal secrets, it is anticipated to use a component sensitive to the activation of a parasitic...
US20090267646 Nano-Electron Fluidic Logic (NFL) Device  
A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with...
US20100308863 Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell Zone  
An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of...
US20090243648 OPTIMAL LOCAL SUPPLY VOLTAGE DETERMINATION CIRCUIT  
A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each...
US20090140766 Signal transmission circuit and characteristic adjustment method thereof, memory module, and manufacturing method of circuit board  
A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a...
US20100045336 Method and Device for Programmable Power Supply with Configurable Restrictions  
The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a...
US20130100993 DUAL MODE POWER AMPLIFIER CONTROL INTERFACE WITH A THREE-MODE GENERAL PURPOSE INPUT/OUTPUT INTERFACE  
In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a...
US20150130510 LEAKAGE REDUCTION IN OUTPUT DRIVER CIRCUITS  
An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically...
US20090267647 Convertible logic circuits comprising carbon nanotube transistors having ambipolar charateristics  
A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a...
US20080007297 Fan abnormality detection device  
When a fan drive current has become excessive, a fan drive device intercepts that current, waits for just a fixed time period T1, and thereafter flows that current for a second time. The fan power...
US20070115026 Load-aware circuit arrangement  
The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the...
US20140028348 Via-Configurable High-Performance Logic Block Involving Transistor Chains  
A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and...
US20070018691 Multi-pad structure for semiconductor device  
A pad layout structure may include a pad and adjacent circuit areas having an electrostatic protection circuit and a data input/output circuit. The pad may be selectively connected to the adjacent...
US20080141186 Semiconductor integrated circuit and design method for semiconductor integrated circuit  
The semiconductor integrated circuit of the invention includes: two first power supply lines placed in parallel in a same interconnect layer; a second power supply line placed between the two...
US20120112788 Phase Change Device for Interconnection of Programmable Logic Device  
A programmable logic device has a configurable interconnection coupling logic blocks, where the configurable interconnection has a phase change element with an amorphous region having a variable...
US20050017756 Dynamic control of physical layer quality on a serial bus  
A control system controls a physical layer quality of user data transmitted between first and second ends of a serial bus. The control system comprises a first line driver that has a control input...
US20150214933 METASTABILITY GLITCH DETECTION  
This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample...
US20080048720 Data transmitters and methods thereof  
In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a...
US20070046328 Self-excited inverter circuit  
A self-excited inverter circuit, includes: a booster transformer with a secondary coil, a feedback coil, and a primary coil respectively wound thereon, the primary coil including a center tap to...
US20060176073 Clocked preconditioning of intermediate nodes  
A clocked bleeder device is used to precondition an intermediate node of an integrated circuit. The clocked bleeder device is activated by a clock signal. The clock signal activates the bleeder...
US20100052729 DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT  
An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained...
US20090256591 STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT  
Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
US20100007701 CERAMIC PRINTED CIRCUIT BOARD (PCB) AND INKJET PRINTHEAD ASSEMBLY USING THE SAME  
A ceramic printed circuit board (PCB) and an inkjet printhead assembly using the ceramic PCB. A ceramic PCB in which a plurality of layers are stacked includes a plurality of terminals to receive...
US20070040582 Inferential power monitor without voltage/current transducers  
A system that facilitates estimating power consumption in a computer system by inferring the power consumption from instrumentation signals. During operation, the system monitors instrumentation...
US20070008003 Self-biased high speed level shifter circuit  
A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter...
US20080204078 LEVEL SHIFTER FOR PREVENTING STATIC CURRENT AND PERFORMING HIGH-SPEED LEVEL SHIFTING  
A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and...
US20080224727 Logic System for Dpa and/or Side Channel Attach Resistance  
DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design...
US20120293199 Programmable Priority Encoder  
In one embodiment, a programmable priority encoder is configured to receive inputs, including an ordered list of a plurality of input request values each representing either a request or a...
US20130257478 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20120105104 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20110084728 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20060261856 Semiconductor chip and semiconductor device incorporating the same  
A semiconductor chip is composed of first and second pads receiving first and second input signals, respectively, a logic circuit, and a circuit block connected to an output of the logic circuit....