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US20070182456 Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form  
An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form...
US20110006810 LOW-SWING CMOS INPUT CIRCUIT  
The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art. The CMOS input circuit according...
US20130314123 LOOKUP TABLE AND PROGRAMMABLE LOGIC DEVICE INCLUDING LOOKUP TABLE  
A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of...
US20100079166 Programmable Signal Routing Systems Having Low Static Leakage  
Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where...
US20090033363 Multi-function input terminal  
A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1)...
US20090009434 High power address driver and display device employing the same  
An address driver includes an energy recovery circuit and an output stage connected to the energy recovery circuit. The output stage is connected to the energy recovery circuit and is formed of a...
US20080218202 Reconfigurable array to compute digital algorithms  
An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is described.
US20080197876 INTEGRATED CIRCUIT, SYSTEM AND METHOD INCLUDING A PERFORMANCE TEST MODE  
An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N...
US20130278285 MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA  
PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors...
US20110062991 ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASYNCHRONOUS INPUTS  
A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a...
US20100019798 SPIN MOSFET AND RECONFIGURABLE LOGIC CIRCUIT USING THE SPIN MOSFET  
It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has...
US20080129330 Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit  
An integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry...
US20070247195 LOW OUTPUT-TO-OUTPUT SKEW/LOW JITTER STAGGERED OUTPUT BUFFER  
A system and method for generating multiple current steered output signals at a centralized location and subsequently routing them to their respective output pads is shown and described. The system...
US20090167357 EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS  
An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding...
US20080278198 Buffer for Object Information  
A buffer that is state-aware and/or node-oriented. In a state-aware buffer, one or more operations relating to a state can be performed. In a node-oriented buffer, instances of a node can be...
US20080048725 Domino Circuit with Master and Slave (DUAL) Pull Down Paths  
A domino circuit and method include a master evaluation node to which a master discharge path with a wide input AND gate is coupled and a virtual evaluation node to which an output stage and slave...
US20070247196 Circuit and method for configuring a circuit  
A circuit and method for configuring a circuit is disclosed. In one embodiment, the circuit includes at least one pull-down path, wherein an amount of a current flowing through the pull-down path...
US20100007375 TERMINATION RESISTANCE CIRCUIT  
A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of...
US20060202719 Semiconductor integrated circuit device and design method thereof  
In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in...
US20090309630 TERNARY VALVE INPUT CIRCUIT  
A pull-up switching device for controlling connection and non-connection of an input terminal IN and a first supply VDD and a pull-down switching device for controlling connection and...
US20100264954 RECEIVE CIRCUIT FOR CONNECTORS WITH VARIABLE COMPLEX IMPEDANCE  
Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a...
US20120217999 Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter  
A low voltage differential signal (LVDS) driving circuit and a digital signal transmitter with the LVDS driving circuit are provided. The LVDS driving circuit includes a positive differential...
US20140043063 SEMICONDUCTOR DEVICE  
A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion...
US20090261859 RECEIVER CIRCUITRY FOR RECEIVING REDUCED SWING SIGNALS FROM A CHANNEL  
A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly...
US20110031996 LOW-JITTER HIGH-FREQUENCY CLOCK CHANNE  
According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock...
US20120112790 Level Shifter  
A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and...
US20090189641 INTEGRATED CIRCUIT DEVICE AND LAYOUT DESIGN METHOD THEREFOR  
An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is connected in the form of a tree...
US20090284279 Integrated Circuit Having Inverse Bit Storage Test  
An integrated circuit is provided having a memory storing first and second strings of bit values, each bit value in the second string being the logical inverse of a bit value at a corresponding bit...
US20060158224 Output driver with feedback slew rate control  
An output driver circuit comprises a primary output driver and a secondary output driver, where the primary and secondary output drivers have outputs at an output terminal and inputs at an input...
US20110273205 RECONFIGURABLE INTEGRATED CIRCUIT  
A reconfigurable integrated circuit has non-volatile storage cells which form a plurality of programmable routing switches between basic tiles. The circuit includes a plurality of non-volatile...
US20100061161 Self Reset Clock Buffer In Memory Devices  
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of...
US20140002136 On-Chip Probe Circuit for Detecting Faults in an FPGA  
An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control...
US20100207658 FAULT TOLERANT ASYNCHRONOUS CIRCUITS  
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event...
US20070296460 Semiconductor apparatus and signal processing system  
A semiconductor apparatus of the present invention includes a first to a fourth external terminals and a decoding circuit. The semiconductor apparatus in a first mode inputs a first encoded data...
US20060087342 Interconnect structure and method in programmable devices  
An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of...
US20060061383 On-chip power regulator for ultra low leakage current  
A low leakage current power regulator is disclosed. The low leakage current power regulator comprises a starter, a leakage holder, a discharger and a linear regulator. The regulator provides a low...
US20120062278 CONFIGURABLE INTEGRATED CIRCUIT WITH BUILT-IN TURNS  
Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100...
US20060001447 Level shifting circuit between isolated systems  
A level shifting circuit (20, 30) couples an input current (Iin) from one system to another, isolated, system, by driving a single load (L) via one or more current mirrors of a common type. In a...
US20130300453 FUEL DISPENSER INPUT DEVICE TAMPER DETECTION ARRANGEMENT  
A system for detecting unauthorized removal or tampering. The system comprises a printed circuit board having tamper-response electronics and a flexible circuit assembly defining a connector...
US20130321027 Circuit Arrangements and Methods of Operating the Same  
In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting...
US20060244478 Systems and methods for reducing signal ringing  
Systems for reducing ringing of a signal generated by a digital signal source circuit include a number of driver circuits configured to incrementally increase an output impedance of the source...
US20090315590 Logic circuits, inverter devices and methods of operating the same  
An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally...
US20080106297 SLEW RATE CONTROLLED CIRCUITS  
A slew rate controlled output buffer. The slew rate controlled output buffer comprises a pre-driver circuit having a data input node and a data output node and a driver circuit coupled to the...
US20070182450 Voltage level shifter circuit  
A level shifter circuit for converting a logic signal with logic ‘1’ and ‘0’ levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In part...
US20080225497 Semiconductor integrated circuit and semiconductor package module having the same  
A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to...
US20130154686 Method and Apparatus for Facilitating Communication Between Programmable Logic Circuit and Application Specific Integrated Circuit with Clock Adjustment  
A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is...
US20090302885 TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING  
A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a...
US20110025373 Semiconductor devices having ZQ calibration circuits and calibration methods thereof  
Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a...
US20070273403 Clock Tree For Programmable Logic Array Devices  
A clock tree for PLAD is provided, with each logic element having an embedded circuit having a buffer connecting vertical bus wires to horizontal bus wires so that the clocks on each horizontal bus...
US20130315005 INPUT BUFFER  
An input buffer which includes an amplification circuit configured to amplify a difference between a first input signal and a second input signal; and an inverter configured to invert an output...