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US20070256041 |
Method and apparatus of core timing prediction
A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any...
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US20080309373 |
INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT
An integrated circuit device includes a clock signal supply control circuit that controls a timing when a master clock signal output from an oscillation circuit is supplied to an internal circuit...
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US20100277202 |
Circuitry and Layouts for XOR and XNOR Logic
An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node...
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US20100201401 |
DECODER CIRCUIT
The present invention provides a decoder circuit that can prevent the delay of decoder output. Namely, a switch that is put into an ON state when a node A of an NMOS region is not an output channel...
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US20100264955 |
METAL PROGRAMMABLE LOGIC AND MULTIPLE FUNCTION PIN INTERFACE
Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a...
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US20100060318 |
Printed circuit board having a termination of a T-shaped signal line
Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the...
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US20080122486 |
Circuit and methodology for high-speed, low-power level shifting
A level shifting circuit and methodology involving a switching current generator responsive to switching of an input signal for producing a switching current to switch an output signal, and a...
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US20070188193 |
Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method
An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This...
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US20110309858 |
NON-VOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME
In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output...
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US20090212817 |
Configuration information writing apparatus, configuration information writing method and computer program product
A configuration information writing apparatus for writing configuration information defining a logical configuration of a logic circuit device into the logic circuit device to change the logical...
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US20120326745 |
Current-Mode Logic Buffer with Enhanced Output Swing
A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being...
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US20060214696 |
Voltage supply structure and method
FIG. 1c shows a logic tree 10c comprising a plurality of logic paths (27, 29, 31, 33) connected at a root 11c. The length of each path represents the delay of the path at a nominal supply voltage....
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US20120299622 |
Internal Clock Gating Apparatus
An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino...
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US20110181320 |
Differential logic circuit, frequency divider, and frequency synthesizer
A differential logic circuit includes: a differential logic unit which receives a plurality of logic signals, performs a logic operation, and outputs a result of the logic operation from a pair of...
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US20100321064 |
COMBINATORIAL CIRCUIT WITH SHORTER DELAY WHEN INPUTS ARRIVE SEQUENTIALLY AND DELTA SIGMA MODULATOR USING THE COMBINATORIAL CIRCUIT
A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate...
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US20090278568 |
METHOD AND SYSTEM TO REDUCE ELECTROMAGNETIC RADIATION FROM SEMICONDUCTOR DEVICES
Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device...
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US20090090908 |
Providing A Duplicate Test Signal Of An Output Signal Under Test In An Integrated Circuit
Providing a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test...
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US20100195374 |
Eight Transistor Soft Error Robust Storage Cell
A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to...
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US20110204918 |
DELAY SIMULATION SYSTEM, DELAY SIMULATION METHOD, PLD MAPPING SYSTEM, PLD MAPPING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT
A delay simulation system comprises an input unit configured to input a netlist, a library, and information including load capacitances; and a simulation unit; the library defines a plurality of...
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US20070247189 |
FIELD PROGRAMMABLE SEMICONDUCTOR OBJECT ARRAY INTEGRATED CIRCUIT
A field-programmable object array integrated circuit employs a course gain architecture comprising a core array of highly optimized silicon objects that are individually programmed and...
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US20070279086 |
ANTIFUSE PROGRAMMING CIRCUIT WITH SNAPBACK SELECT TRANSISTOR
An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the...
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US20110242080 |
Inverter circuit and display
An inverter circuit includes: a first transistor and a second transistor; a first switch and a second switch; and a first capacity element, in which the first and second transistors are connected...
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US20090102778 |
Shift register, gate driving circuit with bi-directional transmission function, and LCD with double frame rate
A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The...
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US20080174339 |
Method and System for Communication Employing Dual Slew Rates
A bus for implementation with a computer system, as well as a computer processing device capable of interacting with such a bus, and a method of communicating signals over a bus, are disclosed. In...
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US20120001654 |
Three Dimensional Multilayer Circuit
A three dimensional multilayer circuit (400) includes a via array (325, 330) made up of a set of first vias (325) and a set of second vias (330) and an area distributed CMOS layer (310) configured...
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US20100060322 |
ADIABATIC CMOS DESIGN
An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first...
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US20080315917 |
Programmable computing array
Methods, devices, and systems for programmable computing arrays have been described. One or more embodiments include programming both a first and a second floating gate of a combined memory and...
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US20120081151 |
DELAY CIRCUIT AND INVERTER FOR SEMICONDUCTOR INTEGRATED DEVICE
An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has...
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US20120139577 |
HACKING DETECTING DEVICE, INTEGRATED CIRCUIT AND METHOD OF DETECTING A HACKING ATTEMPT
A hacking detecting device includes a metal line capacitor, a charge providing unit, a charge storing unit and a hacking deciding unit. The metal line capacitor has a first metal line and a second...
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US20110221469 |
LOGIC BUILT-IN SELF-TEST SYSTEM AND METHOD FOR APPLYING A LOGIC BUILT-IN SELF-TEST TO A DEVICE UNDER TEST
A logic built-in self test (LBIST) system comprises a device under test having a first plurality of first bistable multivibrator circuits an LBIST controller, and a second plurality of second...
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US20090135643 |
SEU HARDENING CIRCUIT AND METHOD
An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors,...
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US20120068733 |
UNIVERSAL FUNCTIONALITY MODULE
Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for...
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US20110085662 |
HIGH UTILIZATION UNIVERSAL LOGIC ARRAY WITH VARIABLE CIRCUIT TOPOLOGY AND LOGISTIC MAP CIRCUIT TO REALIZE A VARIETY OF LOGIC GATES WITH CONSTANT POWER SIGNATURES
Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded...
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US20090302887 |
APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEVICES AND ASSOCIATED METHODS
A programmable logic device (PLD) includes a driver circuit, a configuration memory, and a control circuit. The configuration memory stores driver strength information for the driver circuit. The...
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US20070188187 |
Impedance matching and trimming apparatuses and methods using programmable resistance devices
Impedance matching and trimming apparatuses and methods using programmable resistance devices. According to one exemplary embodiment, the impedance matching circuit includes a programmable...
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US20120235706 |
High speed integrated circuit
A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an...
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US20100001762 |
DOMAIN CROSSING CIRCUIT AND METHOD
A domain crossing circuit for reducing current consumption includes an internal counter to count an internal clock in response to the release of a reset signal, outputting an internal code, a...
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US20090146682 |
DATA OUTPUT DRIVING CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE THEREOF
A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate...
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US20120229167 |
Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors
A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a...
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US20110215830 |
OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD
An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an...
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US20080068042 |
PROGRAMMABLE SYSTEM IN PACKAGE
Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC hou...
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US20080001634 |
Per die temperature programming for thermally efficient integrated circuit (IC) operation
Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC...
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US20100301900 |
Pre-Charged High-Speed Level Shifters
An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled...
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US20060022710 |
Integrated circuit having an input/output terminal configurable within a given voltage range
A circuit disposes of a power supply terminal dedicated to the power supply VIO of the input/output terminals in order that these terminals may be used by a customer in a voltage range of their...
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US20100219859 |
Non-Sequentially Configurable IC
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a...
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US20130033289 |
INPUT AND OUTPUT BUFFER INCLUDING A DYNAMIC DRIVER REFERENCE GENERATOR
A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level...
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US20110254591 |
INPUT AND OUTPUT BUFFER INCLUDING A DYNAMIC DRIVER REFERENCE GENERATOR
A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level...
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US20070247185 |
Memory system with dynamic termination
The termination impedance of a memory agent may be selected dynamically. A transmission line may be simultaneously terminated with a first impedance at first memory agent and a different impedance...
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US20100079167 |
DIFFERENTIAL VOLTAGE MODE DRIVER AND DIGITAL IMPEDANCE CALIBERATION OF SAME
A differential voltage mode driver and digital impedance calibration of same is provided. In one embodiment, the invention relates to a method of calibrating a differential driver circuit having a...
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US20110204922 |
Receiver to Match Delay for Single Ended and Differential Signals
In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two...
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