Sign up


Match Document Document Title
US20090140766 Signal transmission circuit and characteristic adjustment method thereof, memory module, and manufacturing method of circuit board  
A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a...
US20100045336 Method and Device for Programmable Power Supply with Configurable Restrictions  
The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a...
US20130100993 DUAL MODE POWER AMPLIFIER CONTROL INTERFACE WITH A THREE-MODE GENERAL PURPOSE INPUT/OUTPUT INTERFACE  
In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a...
US20150130510 LEAKAGE REDUCTION IN OUTPUT DRIVER CIRCUITS  
An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically...
US20090267647 Convertible logic circuits comprising carbon nanotube transistors having ambipolar charateristics  
A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a...
US20080007297 Fan abnormality detection device  
When a fan drive current has become excessive, a fan drive device intercepts that current, waits for just a fixed time period T1, and thereafter flows that current for a second time. The fan power...
US20070115026 Load-aware circuit arrangement  
The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the...
US20140028348 Via-Configurable High-Performance Logic Block Involving Transistor Chains  
A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and...
US20070018691 Multi-pad structure for semiconductor device  
A pad layout structure may include a pad and adjacent circuit areas having an electrostatic protection circuit and a data input/output circuit. The pad may be selectively connected to the adjacent...
US20080141186 Semiconductor integrated circuit and design method for semiconductor integrated circuit  
The semiconductor integrated circuit of the invention includes: two first power supply lines placed in parallel in a same interconnect layer; a second power supply line placed between the two...
US20120112788 Phase Change Device for Interconnection of Programmable Logic Device  
A programmable logic device has a configurable interconnection coupling logic blocks, where the configurable interconnection has a phase change element with an amorphous region having a variable...
US20050017756 Dynamic control of physical layer quality on a serial bus  
A control system controls a physical layer quality of user data transmitted between first and second ends of a serial bus. The control system comprises a first line driver that has a control input...
US20080048720 Data transmitters and methods thereof  
In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a...
US20070046328 Self-excited inverter circuit  
A self-excited inverter circuit, includes: a booster transformer with a secondary coil, a feedback coil, and a primary coil respectively wound thereon, the primary coil including a center tap to...
US20060176073 Clocked preconditioning of intermediate nodes  
A clocked bleeder device is used to precondition an intermediate node of an integrated circuit. The clocked bleeder device is activated by a clock signal. The clock signal activates the bleeder...
US20100052729 DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT  
An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained...
US20090256591 STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT  
Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
US20100007701 CERAMIC PRINTED CIRCUIT BOARD (PCB) AND INKJET PRINTHEAD ASSEMBLY USING THE SAME  
A ceramic printed circuit board (PCB) and an inkjet printhead assembly using the ceramic PCB. A ceramic PCB in which a plurality of layers are stacked includes a plurality of terminals to receive...
US20070040582 Inferential power monitor without voltage/current transducers  
A system that facilitates estimating power consumption in a computer system by inferring the power consumption from instrumentation signals. During operation, the system monitors instrumentation...
US20070008003 Self-biased high speed level shifter circuit  
A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter...
US20080204078 LEVEL SHIFTER FOR PREVENTING STATIC CURRENT AND PERFORMING HIGH-SPEED LEVEL SHIFTING  
A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and...
US20080224727 Logic System for Dpa and/or Side Channel Attach Resistance  
DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design...
US20120293199 Programmable Priority Encoder  
In one embodiment, a programmable priority encoder is configured to receive inputs, including an ordered list of a plurality of input request values each representing either a request or a...
US20130257478 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20120105104 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20110084728 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20060261856 Semiconductor chip and semiconductor device incorporating the same  
A semiconductor chip is composed of first and second pads receiving first and second input signals, respectively, a logic circuit, and a circuit block connected to an output of the logic circuit....
US20150015305 DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY  
Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified...
US20110241730 Inverter circuit and display  
An inverter circuit includes: first to third transistors; and first and second capacity elements. The first transistor makes/breaks connection between an output terminal and a first voltage line...
US20110241729 Inverter circuit and display  
An inverter circuit includes: first to third transistors; and first and second capacity elements. The first transistor makes/breaks connection between an output terminal and a first voltage line...
US20080211537 Open drain output circuit  
The transition time of an output is sometimes changed by a certain supply voltage connected to an output terminal of an output circuit. An output circuit to address this problem includes: a level...
US20070008004 Apparatus and methods for low-power routing circuitry in programmable logic devices  
An interconnect circuit includes a driver circuit and a receiver circuit. The receiver circuit couples to the driver circuit. The driver circuit is configured to receive an input signal and to...
US20100085081 INVERTER MANUFACTURING METHOD AND INVERTER  
To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in...
US20090080276 Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits  
A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the...
US20100001757 INTEGRATED CIRCUIT AND METHOD OF PROTECTING A CIRCUIT PART TO BE PROTECTED OF AN INTEGRATED CIRCUIT  
A integrated circuit comprises a circuit part to be protected and protective lines located at least one wiring level of the integrated circuit. In addition, the integrated circuit comprises...
US20110133779 INTERFACE CIRCUIT  
An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a...
US20110133775 INTERFACE CIRCUIT  
An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a...
US20140055164 BUFFER SYSTEM HAVING REDUCED THRESHOLD CURRENT  
A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management...
US20090309628 SEMICONDUCTOR MEMORY DEVICE AND ON-DIE TERMINATION CIRCUIT  
An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each...
US20090140772 ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES  
Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging...
US20090271135 Detecting Device for Detecting an Operating Mode of a System and Detecting Method Thereof  
A detecting device for detecting an operating mode is disclosed. The detecting device includes a pulse generator and a hold-up unit. The pulse generator is disposed for issuing a one-shot pulse...
US20110199121 SMART EDGE DETECTOR  
In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D2) to trigger a first flip-flop having a first clock in a...
US20110240737 ELECTRONIC DEVICE AND PROTECTION MECHANISM THEREOF  
An electronic device includes a protection mechanism, a first circuit board having a first electronic loop, and a second circuit board having a second electronic loop. The protection mechanism is...
US20090309627 Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits  
The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention,...
US20130115907 VARIABLE DUTY-CYCLE MULTI-STANDARD MIXER  
An adjustable mixer is disclosed that is capable of operating in different modes in order to satisfy the mixing requirement of multiple radio access technologies (RATs). The adjustable mixer...
US20120262200 HIGH DEFINITION MULTIMEDIA INTERFACE (HDMI) APPARATUS INCLUDING TERMINATION CIRCUIT  
A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The...
US20130093462 CONFIGURABLE STORAGE ELEMENTS  
A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that...
US20100060311 CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES  
An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks...
US20100176840 SUPERCONDUCTIVE CROSSBAR SWITCH  
A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with...
US20100148818 HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT  
A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage...