Sign up


Match Document Document Title
US20100007701 CERAMIC PRINTED CIRCUIT BOARD (PCB) AND INKJET PRINTHEAD ASSEMBLY USING THE SAME  
A ceramic printed circuit board (PCB) and an inkjet printhead assembly using the ceramic PCB. A ceramic PCB in which a plurality of layers are stacked includes a plurality of terminals to receive...
US20070040582 Inferential power monitor without voltage/current transducers  
A system that facilitates estimating power consumption in a computer system by inferring the power consumption from instrumentation signals. During operation, the system monitors instrumentation...
US20070008003 Self-biased high speed level shifter circuit  
A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter...
US20080204078 LEVEL SHIFTER FOR PREVENTING STATIC CURRENT AND PERFORMING HIGH-SPEED LEVEL SHIFTING  
A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and...
US20080224727 Logic System for Dpa and/or Side Channel Attach Resistance  
DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design...
US20120293199 Programmable Priority Encoder  
In one embodiment, a programmable priority encoder is configured to receive inputs, including an ordered list of a plurality of input request values each representing either a request or a...
US20130257478 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20120105104 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20110084728 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20060261856 Semiconductor chip and semiconductor device incorporating the same  
A semiconductor chip is composed of first and second pads receiving first and second input signals, respectively, a logic circuit, and a circuit block connected to an output of the logic circuit....
US20150015305 DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY  
Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified...
US20110241730 Inverter circuit and display  
An inverter circuit includes: first to third transistors; and first and second capacity elements. The first transistor makes/breaks connection between an output terminal and a first voltage line in...
US20110241729 Inverter circuit and display  
An inverter circuit includes: first to third transistors; and first and second capacity elements. The first transistor makes/breaks connection between an output terminal and a first voltage line in...
US20080211537 Open drain output circuit  
The transition time of an output is sometimes changed by a certain supply voltage connected to an output terminal of an output circuit. An output circuit to address this problem includes: a level...
US20070008004 Apparatus and methods for low-power routing circuitry in programmable logic devices  
An interconnect circuit includes a driver circuit and a receiver circuit. The receiver circuit couples to the driver circuit. The driver circuit is configured to receive an input signal and to...
US20100085081 INVERTER MANUFACTURING METHOD AND INVERTER  
To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in...
US20090080276 Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits  
A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the...
US20100001757 INTEGRATED CIRCUIT AND METHOD OF PROTECTING A CIRCUIT PART TO BE PROTECTED OF AN INTEGRATED CIRCUIT  
A integrated circuit comprises a circuit part to be protected and protective lines located at least one wiring level of the integrated circuit. In addition, the integrated circuit comprises logical...
US20110133779 INTERFACE CIRCUIT  
An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a...
US20110133775 INTERFACE CIRCUIT  
An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a...
US20140055164 BUFFER SYSTEM HAVING REDUCED THRESHOLD CURRENT  
A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management...
US20090309628 SEMICONDUCTOR MEMORY DEVICE AND ON-DIE TERMINATION CIRCUIT  
An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each...
US20090140772 ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES  
Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging...
US20090271135 Detecting Device for Detecting an Operating Mode of a System and Detecting Method Thereof  
A detecting device for detecting an operating mode is disclosed. The detecting device includes a pulse generator and a hold-up unit. The pulse generator is disposed for issuing a one-shot pulse...
US20110199121 SMART EDGE DETECTOR  
In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D2) to trigger a first flip-flop having a first clock in a...
US20110240737 ELECTRONIC DEVICE AND PROTECTION MECHANISM THEREOF  
An electronic device includes a protection mechanism, a first circuit board having a first electronic loop, and a second circuit board having a second electronic loop. The protection mechanism is...
US20090309627 Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits  
The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention,...
US20130115907 VARIABLE DUTY-CYCLE MULTI-STANDARD MIXER  
An adjustable mixer is disclosed that is capable of operating in different modes in order to satisfy the mixing requirement of multiple radio access technologies (RATs). The adjustable mixer...
US20120262200 HIGH DEFINITION MULTIMEDIA INTERFACE (HDMI) APPARATUS INCLUDING TERMINATION CIRCUIT  
A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias...
US20130093462 CONFIGURABLE STORAGE ELEMENTS  
A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that...
US20100060311 CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES  
An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks...
US20100176840 SUPERCONDUCTIVE CROSSBAR SWITCH  
A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with...
US20100148818 HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT  
A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage...
US20120112786 MICRO-GRANULAR DELAY TESTING OF CONFIGURABLE ICS  
A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method...
US20110068820 Micro-Granular Delay Testing of Configurable ICs  
A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method...
US20140306736 STATE MACHINE CIRCUIT AND STATE ADJUSTING METHOD  
A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value,...
US20080231317 Staggered logic array block architecture  
A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of...
US20140285232 Methods and Systems for Reducing Supply and Termination Noise  
Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the...
US20120182044 Methods and Systems for Reducing Supply and Termination Noise  
Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the...
US20080288906 Integrated system on module  
An electronic product includes a circuit board, an integrated system on module, and an application-specific module. The integrated system on module and the application-specific module are...
US20080222592 SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD  
A semiconductor integrated circuit including a user logic circuit is disclosed in which circuit parts for shifting data are composed of registers other than scan cells except for the circuit part...
US20070103185 Dual path redundancy with stacked transistor voting  
A method of operation and an apparatus for radiation hardening a combinational logic circuit are presented. A section of logic that is to be radiation hardened is identified. An entire logic...
US20140232430 METHODS AND SYSTEMS TO STRESS-PROGRAM AN INTEGRATED CIRCUIT  
Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program,...
US20120286822 AUTOMATED METAL PATTERN GENERATION FOR INTEGRATED CIRUCITS  
An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the...
US20070176640 Dynamic circuit  
The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a...
US20090134912 ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS  
A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an...
US20150008955 METHOD AND APPARATUS FOR SUPPORTING SELF-DESTRUCTION FUNCTION IN BASEBAND MODEM  
A method and an apparatus for supporting a self-destruction function in a baseband modem are provided. A self-destruction method of a baseband modem includes sending a request for supplying power...
US20070176641 Low swing domino logic circuits  
Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper...
US20130278287 Low Leakage Boundary Scan Device Design and Implementation  
A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving...
US20080169842 DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT  
A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated...