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US20090302894 |
DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC
A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The...
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US20090230994 |
DOMINO LOGIC CIRCUIT AND PIPELINED DOMINO LOGIC CIRCUIT
A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of...
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US20090206881 |
SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate...
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US20090167358 |
FULLY INTERRUPTIBLE DOMINO LATCH
A domino latch is provided that comprises a forward path circuit and a feedback path circuit. The feedback path includes a plurality of keeper transistors, an inverter, and at least one interrupt...
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US20090146734 |
Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits
In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep...
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US20080258771 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors...
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US20080174340 |
OPTIMIZED CHARGE SHARING FOR DATA BUS SKEW APPLICATIONS
A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one...
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US20080100344 |
SCANNABLE DYNAMIC LOGIC LATCH CIRCUIT
A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a...
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US20080048725 |
Domino Circuit with Master and Slave (DUAL) Pull Down Paths
A domino circuit and method include a master evaluation node to which a master discharge path with a wide input AND gate is coupled and a virtual evaluation node to which an output stage and slave...
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US20080036502 |
ACCELERATED P-CHANNEL DYNAMIC REGISTER
A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal,...
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US20080036501 |
ACCELERATED N-CHANNEL DYNAMIC REGISTER
A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal,...
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