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US20110037498 VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS  
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI...
US20140347096 NON-LUT FIELD-PROGRAMMABLE GATE ARRAYS  
New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new...
US20140097868 FINE GRAIN PROGRAMMABLE GATE ARCHITECTURE WITH HYBRID LOGIC/ROUTING ELEMENT AND DIRECT-DRIVE ROUTING  
An apparatus is disclosed herein for a programmable gate architecture with hybrid logic/routing circuitry. In one embodiment, a programmable gate array comprises a plurality of hybrid logic or...
US20110148462 Post-Programming Functional Verification for Programable Integrated Circuits  
Techniques and technology are provided to enable the testing of a programmable integrated circuit from within the programmable integrated circuit itself. In various implementations of the...
US20150035562 LOOK-UP TABLE ARCHITECTURE  
The present invention relates to a look-up table architecture and to an FPGA comprising the same. The look-up table architecture comprises a registers group comprising a plurality of registers...
US20140167815 AREA RECONFIGURABLE CELLS OF A STANDARD CELL LIBRARY  
An integrated circuit using area reconfigurable cells of a standard cell library includes standard cells placed adjacent with one another in rows and columns. Each of the standard cells has a...
US20070164784 Modular I/O bank architecture  
A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O...
US20120182046 TIMING OPERATIONS IN AN IC WITH CONFIGURABLE CIRCUITS  
Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC)....
US20090009215 Integrated Circuit with Multidimensional Switch Topology  
An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high...
US20130063178 LOGIC CELLS BASED ON SPIN DIODE AND APPLICATIONS OF SAME  
In one aspect, the invention relates to logic cells that utilize one or more of spin diodes. By placing one or two control wires on the side of the spin diodes to generate magnetic fields in the...
US20130009667 SUB-THRESHOLD FPGA AND RELATED CIRCUITS AND METHODS THEREOF  
A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low...
US20110084727 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS  
Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of...
US20110260752 GENERAL PURPOSE INPUT/OUTPUT PIN MAPPING  
An I/O pin mapping module integrated on a microcontroller chip allows any microcontroller circuit node connected to the I/O pin mapping module to be mapped to any microcontroller I/O pin connected...
US20150214950 PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA  
A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of...
US20110199119 PROGRAMMABLE LOGIC DEVICE WITH CUSTOM BLOCKS  
A programmable logic device is described, comprising a uniform routing network, an array of user programmable tiles connected to the uniform routing network and at least one functional block...
US20110050282 ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS  
An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs).
US20150130508 Non-Sequentially Configurable IC  
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a...
US20110267102 NON-SEQUENTIALLY CONFIGURABLE IC  
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a...
US20150130509 NANOELECTROMECHANICAL ANTIFUSE AND RELATED SYSTEMS  
An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air...
US20110298492 Adjustable Interface Buffer Circuit Between A Programmable Logic Device And A Dedicated Device  
An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different...
US20130009666 FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC  
A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or...
US20120326749 INTERCONNECTED ARRAY OF LOGIC CELLS RECONFIGURABLE WITH INTERSECTING INTERCONNECTION TOPOLOGY  
An interconnected array of reconfigurable logic cells which carry out at least one logic function, externally connected to peripheral connection network equipped with switch boxes and connected to...
US20090219051 HYBRID NANOTUBE/CMOS DYNAMICALLY RECONFIGURABLE ARCHITECTURE AND AN INTEGRATED DESIGN OPTIMIZATION METHOD AND SYSTEM THEREFOR  
A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture...
US20120280712 SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC  
A L-level permutable switching network (L-PSN) having switches and multiple levels of conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
US20110304354 UNIVERSAL DIGITAL BLOCK INTERCONNECTION AND CHANNEL ROUTING  
A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other mirco-controller elements, peripherals and external Inputs...
US20140125378 LOGIC DEVICE AND OPERATING METHOD THEREOF  
A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks...
US20130162292 NON-LUT FIELD-PROGRAMMABLE GATE ARRAYS  
New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new...
US20110248744 SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC  
A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
US20110089972 SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC  
A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
US20150253755 COUNTER OPERATION IN A STATE MACHINE LATTICE  
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable...
US20090289661 Integrated Circuit With Crosslinked Interconnect Networks  
The present invention provides in a first aspect a programmable interconnect network for an array of logic blocks, which comprises a plurality of switch boxes being connected in a tree-based...
US20110234258 ENHANCED FILED PROGRAMMABLE GATE ARRAY  
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same...
US20090128188 Pad invariant FPGA and ASIC devices  
A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having...
US20100090720 FLEXIBLE PARALLEL/SERIAL RECONFIGURABLE ARRAY CONFIGURATION SCHEME  
A programming interface device for a programmable logic circuit, the programmable logic circuit comprising a series of parallel logic block chains each having first and second connection means,...
US20100231256 SPARE CELL LIBRARY DESIGN FOR INTEGRATED CIRCUIT  
A cell based design layout of an application specific integrated circuit (ASIC) having a function has reduceddecreased power leakage because functionally unconnected additional cells or spare...
US20090261858 PROGRAMMABLE INTERCONNECT NETWORK FOR LOGIC ARRAY  
A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its...
US20130135008 METHOD AND SYSTEM FOR A RUN-TIME RECONFIGURABLE COMPUTER ARCHITECTURE  
A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of...
US20070120576 Look-Up Table Action  
A first block represents a two or three dimensional object in a Computer Aided Design (CAD) model, and has a visual presentation in a presentation of the CAD model based on a first plurality of...
US20130135009 METHOD AND APPARATUS FOR IDENTIFYING CONNECTIONS BETWEEN CONFIGURABLE NODES IN A CONFIGURABLE INTEGRATED CIRCUIT  
Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of...
US20110163781 METHOD AND APPARATUS FOR IDENTIFYING CONNECTIONS BETWEEN CONFIGURABLE NODES IN A CONFIGURABLE INTEGRATED CIRCUIT  
Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of...
US20120306534 PROGRAMMABLE LOGIC BASED ON A MAGNETIC DIODE AND APPLICATIONS OF SAME  
In one aspect, the invention relates to programmable logic that utilizes one or more of magnetic diodes. By changing magnetic fields generated in the magnetic diodes due to input signals, the...
US20140333345 Configurable Storage Elements  
Some embodiments provide a configurable integrated circuit (IC) having a routing fabric that includes configurable storage element in its routing fabric. In some embodiments, the configurable...
US20140368236 MULTIPLE-VOLTAGE PROGRAMMABLE LOGIC FABRIC  
One embodiment relates to an integrated circuit including a multiple-voltage programmable logic fabric. The programmable logic fabric includes circuits of a first type operating in a first voltage...
US20140210515 PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS  
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
US20130214815 PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS  
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
US20120217998 PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS  
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
US20140125379 SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE  
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that...
US20120319730 SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE  
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that...
US20140097869 HETEROGENEOUS SEGMENTED AND DIRECT ROUTING ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAY  
A method and apparatus is disclosed herein for segmented and direct routing in a programmable gate array. In one embodiment, the programmable gate array comprises a plurality of programmable...
US20080074142 Routing for Microprocessor Busses  
This invention provides means and methods for improving the routing and multiplexing logic of microprocessor busses and other similar high fan logic functions in FPGA and ASIC circuits. Routing of...
Matches 1 - 50 out of 294 1 2 3 4 5 6 >