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US20090321789 Triangle two dimensional complementary patterning of pillars  
A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three...
US20090321791 Integrated Circuits, Standard Cells, and Methods for Generating a Layout of an Integrated Circuit  
An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially...
US20090321709 MEMORY ELEMENT, MEMORY APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT  
A memory element comprises a first electrode, a second electrode, and a resistance variable film 2 which is disposed between the first and second electrodes to be connected to the first and...
US20090309136 SEA-OF-FINS STRUCTURE OF A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION  
A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin...
US20090289371 SWITCHING ELEMENT AND METHOD OF MANUFACTURING THE SAME  
A switching element includes a first electrode, a second electrode, an ionic conductive portion and a buffer portion. The first electrode is configured to be available to feed metal ions. The ionic...
US20090283868 Structure Replication Through Ultra Thin Layer Transfer  
Methods and apparatus for forming a product from ultra thin layers of a base material are disclosed. Some embodiments provide a process that allows one to structure a silicon base material, like...
US20090273052 Reducing Device Performance Drift Caused by Large Spacings Between Action Regions  
A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in...
US20090273007 Method Of Testing An Integrated Circuit Die, And An Integrated Circuit Die  
In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in...
US20090250782 SUBGROUNDRULE SPACE FOR IMPROVED METAL HIGH-K DEVICE  
The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate...
US20090242994 HYBRID TRANSISTOR BASED POWER GATING SWITCH CIRCUIT AND METHOD  
A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the...
US20090236637 POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE  
An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal...
US20090224242 ISOLATION CIRCUIT  
An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the...
US20090207649 VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY  
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and...
US20090200633 SEMICONDUCTOR STRUCTURES WITH DUAL ISOLATION STRUCTURES, METHODS FOR FORMING SAME AND SYSTEMS INCLUDING SAME  
A semiconductor structure with dual isolation structures is disclosed. The semiconductor structure may include a protruding isolation structure in a pixel array region of a substrate and an...
US20090189194 Electrostatic Discharge (ESD) Protection Circuit Placement in Semiconductor Devices  
Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an...
US20090189195 Radio Frequency (RF) Circuit Placement in Semiconductor Devices  
Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an...
US20090173972 SEMICONDUCTOR DEVICE  
In a substrate power supply cell, a portion of a substrate power supply wiring is exposed by forming a power supply wiring in a U-shape, and a connection portion to an upper-layer wiring is...
US20090166620 SEMICONDUCTOR CHIP  
In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the...
US20090166682 METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY  
The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint...
US20090152592 STRUCTURE FOR A LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA  
A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a...
US20090152591 Design Structure for an On-Demand Power Supply Current Modification System for an Integrated Circuit  
A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively...
US20090152594 On-Demand Power Supply Current Modification System and Method for an Integrated Circuit  
A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin...
US20090121296 Semiconductor device including dummy gate part and method of fabricating the same  
In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as...
US20090085069 NAND-type Flash Array with Reduced Inter-cell Coupling Resistance  
In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of...
US20090085148 MULTI-DIRECTIONAL TRENCHING OF A PLURALITY OF DIES IN MANUFACTURING SUPERJUNCTION DEVICES  
A method of manufacturing a superjunction device includes providing a semiconductor wafer having a plurality of dies. A first plurality of trenches having a first orientation are formed in a first...
US20090078967 SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE HAVING A PLURALITY OF SEMICONDUCTOR CHIPS  
The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without...
US20090072274 INTEGRATED CIRCUIT INCLUDING A FIRST GATE STACK AND A SECOND GATE STACK AND A METHOD OF MANUFACTURING  
An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack...
US20090057743 Integrated Circuit Including Structures Arranged at Different Densities and Method of Forming the Same  
A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the...
US20090026503 SEMICONDUCTOR DEVICE  
CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer...
US20090026502 VIA ANTENNA FIX IN DEEP SUB-MICRON CIRCUIT DESIGNS  
A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler...
US20090009444 MEMS DEVICES HAVING IMPROVED UNIFORMITY AND METHODS FOR MAKING THEM  
Disclosed is a microelectromechanical system (MEMS) device and method of manufacturing the same. In one aspect, MEMS such as an interferometric modulator include one or more elongated interior...
US20080303115 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor memory device includes a semiconductor substrate having a dummy cell region adjacent to a memory cell region, a plurality of memory cell transistors, a selective gate transistor, a...
US20080290375 INTEGRATED CIRCUIT FOR VARIOUS PACKAGING MODES  
The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The...
US20080277693 IMAGER ELEMENT, DEVICE AND SYSTEM WITH RECESSED TRANSFER GATE  
An imager element, device and imaging system image sensor pixel. The image sensor pixel includes a collection region, a floating diffusion region, and a transfer transistor having a recessed gate....
US20080251824 Semiconductor memory device and manufacturing method thereof  
A semiconductor memory device and a manufacturing method thereof are provided which enable cell-contact plugs to be formed at high yields and the yields of semiconductor memory devices to be...
US20080237876 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device...
US20080237647 Integrated Circuits and Methods with Two Types of Decoupling Capacitors  
Methods and systems for optimal decoupling capacitance in a dual-voltage power-island architecture. In low-voltage areas of the chip, accumulation capacitors of two different types are used for...
US20080237599 MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT  
A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor....
US20080224176 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely...
US20080217656 I/O CIRCUIT WITH ESD PROTECTING FUNCTION  
For ensuring the complete turn-off state of an ESD protecting device and preventing leakage current from a chip, an alternative conducting path is formed in the chip for bypassing an external...
US20080217658 ELECTRICAL ANTIFUSE WITH INTEGRATED SENSOR  
The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and...
US20080210978 SEMICONDUCTOR DEVICE  
A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the...
US20080211053 Superjunction Semiconductor Device  
In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of...
US20080211037 Semiconductor Device and Method of Forming Isolation Layer Thereof  
A method of forming an isolation layer of a semiconductor device includes the steps of forming a gate insulating layer and a conductive layer on an active area of a semiconductor substrate; forming...
US20080203438 DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS  
A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2 N semiconductor regions which are parallel to one another and run in a first...
US20080185614 Integrated Circuit Assembly with Passive Integration Substrate for Power and Ground Line Routing on Top of an Integrated Circuit Chip  
An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S 1 ) having a core with input and/or output pins and at least one power supply connection pad (PP) and...
US20080173899 SEMICONDUCTOR DEVICE  
There is provided a technology which allows sufficient protection of internal circuits from electrostatic discharge even when internal-circuit power source pads and internal-circuit GND pads are...
US20080169488 DEVICE SELECTION CIRCUITRY CONSTRUCTED WITH NANOTUBE TECHNOLOGY  
A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a...
US20080169487 LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT  
In a layout structure of a semiconductor integrated circuit, when transistors are arranged in a constant gate wiring pitch, a common source diffusion region is provided between two adjacent...
US20080164496 Semiconductor Integrated Circuit  
When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be...
Matches 1 - 50 out of 65 1 2 >