Matches 1 - 50 out of 72 1 2 >
Match Document Document Title
US20090291528 Semiconductor Package Having Through-Hole Vias on Saw Streets Formed with Partial Saw  
A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die. A trench is formed between the semiconductor die. The trench...
US20090291527 Semiconductor Package Having Through-Hole Vias on Saw Streets Formed with Partial Saw  
A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die. The...
US20090286396 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A STEPPED THROUGH-HOLE  
A DRAM device includes a contact plug in contact with a diffused region of a semiconductor substrate, and a via-plug in contact with top of the contact plug. The through-hole receiving the via-plug...
US20090286395 Butted Source Contact and Well Strap  
A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region...
US20090283909 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a...
US20090283143 POINT CONTACT SOLAR CELL  
A semiconductor component comprises a semiconductor substrate comprising a front surface, a back surface which is opposite thereto, and a surface normal which is perpendicular to the front and back...
US20090278261 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating film. A liner insulating film is...
US20090278178 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
Disclosed is a semiconductor device which includes a MIS FET on a surface of a substrate, an insulating film on the substrate to cover the MIS FET, an opening that gets to an impurity diffusing...
US20090275195 Interconnect Structure Having a Silicide/Germanide Cap Layer  
An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the...
US20090275180 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE  
A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is...
US20090275176 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device...
US20090267181 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device with a fuse 3 a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first...
US20090263964 INTERCONNECTIONS FOR INTEGRATED CIRCUITS  
An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described....
US20090263951 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE  
A method for fabricating a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate, forming a plurality of wiring trenches in the insulating film, forming...
US20090250819 METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME  
The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an...
US20090246951 METHOD FOR PATTERNING A METALLIZATION LAYER BY REDUCING RESIST STRIP INDUCED DAMAGE OF THE DIELECTRIC MATERIAL  
By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the...
US20090233438 SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING  
A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and...
US20090231899 PHASE CHANGE RANDOM ACCESS MEMORY AND LAYOUT METHOD OF THE SAME  
A phase change random access memory (PRAM) includes a cell array divided into an active region and a dummy active region. A bitline is formed across the active region and the dummy active region...
US20090230557 Semiconductor Device and Method for Making Same  
One or more embodiments are related to a semiconductor device, comprising: a metallic layer having a top surface and a sidewall surface; an intermediate layer disposed on a sidewall surface of the...
US20090186431 LIGHT-EMITTING DEVICE AND ITS MANUFACTURING METHOD  
In a light-emitting device and its manufacturing method, mounting by batch process with surface-mount technology, high light extraction efficiency, and low manufacturing cost are realized. The...
US20090184400 VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE  
Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a...
US20090176348 REMOVABLE LAYER MANUFACTURING METHOD  
A method ( 200 ) is described for an electronic assembly ( 30 ). An electronic die ( 24 ) with a sacrificial layer ( 28 ) on its back ( 27 ) and electrical contacts ( 26 ) on its front ( 25 ) is...
US20090170314 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE  
A method for manufacturing a semiconductor device includes the steps of: (a) forming a low dielectric constant film over a semiconductor substrate; (b) forming a recess in the low dielectric...
US20090163029 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
A method of manufacturing a semiconductor device has forming a first nitride layer over a substrate, forming a first oxide layer on the first nitride layer, forming a second nitride layer on the...
US20090160064 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE  
A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an...
US20090159883 TEST PATTERN FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE TEST PATTERN  
A test pattern for a semiconductor device and a method for forming the test pattern that can determine the degree of over etching of contact holes and obviate the need to perform a physical...
US20090146309 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner...
US20090141533 METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE  
A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor...
US20090140437 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF  
A semiconductor device including an intermediate insulating film formed over a plurality of first conductors over a semiconductor substrate. Contact holes are formed in the intermediate insulating...
US20090093120 HOLE PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD  
A hole pattern forming method that forms a fine hole pattern in a work target layer that is formed on a semiconductor substrate, includes: forming a three-layer structure by laminating a carbon...
US20090075474 METHODS FOR FORMING DUAL DAMASCENE WIRING USING POROGEN CONTAINING SACRIFICIAL VIA FILLER MATERIAL  
Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer...
US20090068833 METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE  
The present invention relates to a method of forming a contact hole of a semiconductor device. According to the method of forming a contact hole of a semiconductor device, a semiconductor substrate...
US20090035940 COPPER METALLIZATION OF THROUGH SILICON VIA  
A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an...
US20090032964 System and method for providing semiconductor device features using a protective layer  
Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising...
US20090032963 SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS AND METHODS TO FORM SAME  
Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and...
US20080318413 METHOD FOR MAKING AN INTERCONNECT STRUCTURE AND INTERCONNECT COMPONENT RECOVERY PROCESS  
A method is provided for making an interconnect structure. The method includes applying a removable layer to an electronic device or to a base insulative layer; applying an adhesive layer to the...
US20080315353 EMPTY VIAS FOR ELECTROMIGRATION DURING ELECTRONIC-FUSE RE-PROGRAMMING  
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer...
US20080305627 METHOD OF FORMING A CONTACT PLUG AND METHOD OF FORMING A SEMICONDUCTOR DEVICE  
A method of forming a contact plug includes the following processes. A dummy film is formed over a substrate. The dummy film may include amorphous carbon as a main material. At least one contact...
US20080303097 Power FET With Low On-Resistance Using Merged Metal Layers  
In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over...
US20080299718 DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS  
A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer...
US20080284027 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first...
US20080272476 Through-Hole Via On Saw Streets  
A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide...
US20080237858 ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME  
An electronic device includes a conductive pattern formed on a first insulating film, a second insulating film formed on the conductive pattern and the first insulating film, a hole formed in the...
US20080233743 Method and Structure for Self-Aligned Device Contacts  
Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield....
US20080233737 METHOD OF FABRICATING INTERGRATED CIRCUIT CHIP  
A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and...
US20080206984 CONDUCTIVE VIA FORMATION UTILIZING ELECTROPLATING  
A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side...
US20080206929 PRINTING DEVICE, PRODUCTION UNIT, AND PRODUCTION METHOD OF ELECTRONIC PARTS  
A printing device, a production unit and a production method of electronic parts suitable for production of precise electronic parts are provided. A squeegee is attached to a rotating machine, and...
US20080185730 MEMORY CELL DEVICE WITH COPLANAR ELECTRODE SURFACE AND METHOD  
A memory device described herein includes a bit line having a top surface and a plurality of vias. The device includes a plurality of first electrodes each having top surfaces coplanar with the top...
US20080179755 STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER  
A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch,...
US20080176404 Method for fabricating semiconductor device  
The method for fabricating the semiconductor device comprises the step of forming an insulating film 14 having an opening 18; the step of forming an organic resist film 20 a; the step of...
Matches 1 - 50 out of 72 1 2 >