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US20090286333 |
ETCHING METHOD AND ETCHING APPARATUS OF SEMICONDUCTOR WAFER
A method of etching a semiconductor wafer is provided. The method comprises the steps of: jetting a mixed gas including hydrogen fluoride and ozone onto a surface of a semiconductor wafer;...
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US20090286332 |
POLISHING METHOD
A method for polishing a substrate having a metal film thereon is described. The substrate has metal interconnects formed from part of the metal film. The polishing method includes performing a...
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US20090269862 |
ALIGNMENT METHOD OF CHIPS
An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding...
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US20090269685 |
Position aligning apparatus, position aligning method, and semiconductor device manufacturing method
A position aligning apparatus performs position alignment of a pattern in a current process of a pattern exposure process by using a pattern formed before the current process. The position aligning...
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US20090253222 |
Etching process state judgment method and system therefor
An etching process state judgment method comprising: a spectral data obtaining step, in which an optical emission spectrum distribution is obtained by monitoring optical emission during an etching...
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US20090246892 |
SENSOR, METHOD, AND DESIGN STRUCTURE FOR A LOW-K DELAMINATION SENSOR
The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor...
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US20090239313 |
Integrated Circuit Chip Design Flow Methodology Including Insertion of On-Chip or Scribe Line Wireless Process Monitoring and Feedback Circuitry
Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring...
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US20090197353 |
METHOD OF MANUFACTURING MATERIAL TO BE ETCHED
A method is provided, of manufacturing a material to be etched that can more preferably prevent a region to be etched from remaining as an un-etched region and reduce deviation of etched/un-etched...
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US20090148965 |
Method and apparatuses for high pressure gas annealing
Novel methods and apparatuses for annealing semiconductor devices in a high pressure gas environment. According to an embodiment, the annealing vessel has a dual chamber structure, and potentially...
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US20090142860 |
SYSTEM AND METHOD FOR ENHANCED CONTROL OF COPPER TRENCH SHEET RESISTANCE UNIFORMITY
A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring...
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US20090083592 |
SEMICONDCUTOR DEVICE, MEMORY SYSTEM AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a...
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US20090000995 |
GOOD CHIP CLASSIFYING METHOD ON WAFER, AND CHIP QUALITY JUDGING METHOD, MARKING MECHANISM, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE GOOD CHIP CLASSIFYING METHOD
In a disclosed good chip classifying method capable of classifying the good chips on a wafer, defective chips are divided into defective groups so that the defective chips contiguous to each other...
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US20080311686 |
Method of Forming Semiconductor Layers on Handle Substrates
A method of making a semiconductor thin film bonded to a handle substrate includes implanting a semiconductor substrate with a light ion species while cooling the semiconductor substrate, bonding...
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US20080299684 |
METHOD AND SYSTEM FOR REMOVING EMPTY CARRIERS FROM PROCESS TOOLS BY CONTROLLING AN ASSOCIATION BETWEEN CONTROL JOBS AND CARRIER
By providing an under-specified specification for designating a destination carrier in a respective control job or control message, a high degree of flexibility in determining the destination of...
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US20080233663 |
SINGULATED BARE DIE TESTING
There is testing of individual dice prior to their inclusion in a multi-chip package. A wafer is sawn into individual dice and the dice are placed onto a die tray. If the tray is not full, then...
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US20080227224 |
Method of manufacturing semiconductor device and control system
When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist...
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US20080224330 |
Power delivery package having through wafer vias
An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground...
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US20080224134 |
Test Structures for Identifying an Allowable Process Margin for Integrated Circuits and Related Methods
A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines...
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US20080223298 |
RECOVERY PROCESSING METHOD TO BE ADOPTED IN SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING APPARATUS AND PROGRAM
The present invention provides a recovery processing method to restore the substrate processing apparatus to an operating state after correcting an abnormality having occurred in the substrate...
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US20080191729 |
Thermal interface for electronic chip testing
An apparatus that performs electrical testing is described. This apparatus includes a first semiconductor die that is to be tested, and a connector configured to be coupled to a first surface of...
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US20080188016 |
Die detection and reference die wafermap alignment
One embodiment of the present invention includes a method for aligning a wafermap with a semiconductor wafer. The method may comprise assigning a location code to each of a plurality of dies on the...
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US20080163139 |
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PREPARING MULTIPLE LAYERS OF SEMICONDUCTOR SUBSTRATES FOR ELECTRONIC DESIGNS
Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the...
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US20080157078 |
Metrology Structure And Methods
A method of indicating the progress of a sacrificial material removal process, the method, comprising; freeing a portion of a member, the member being disposed in a cage and laterally surrounded by...
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US20080157077 |
Integrated Circuit and Methods of Measurement And Preparation of Measurement Structure
A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for...
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US20080128693 |
Reliability test structure for multilevel interconnect
Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An...
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US20080096294 |
INTEGRATED CIRCUIT STRUCTURE, DISPLAY MODULE, AND INSPECTION METHOD THEREOF
An integrated circuit structure has an IC chip, at least a functional bump, and at least a dummy bump positioned on a joint surface of the IC chip. A terminal surface of the dummy bump is different...
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US20080070408 |
Method for adjusting sizes and shapes of plug openings
The invention is directed to a method for adjusting sizes and shapes of plug openings for border plug openings overlapping with trenches respectively, wherein the border plug openings are separated...
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US20080057599 |
FABRICATION METHOD OF SEMICONDUCTOR DEVICE
A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a...
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US20080054191 |
NOVEL WAFER REPAIR METHOD USING DIRECT-WRITING
A method of wafer repairing comprises identifying locations and patterns of defective regions in a semiconductor wafer; communicating the locations and patterns of defective regions to a...
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US20080032426 |
METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS
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US20080027577 |
FEATURE DIMENSION DEVIATION CORRECTION SYSTEM, METHOD AND PROGRAM PRODUCT
A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a...
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