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Match Document Document Title
US20120146227 INTEGRATED CIRCUIT NANOWIRES  
Implementations of encapsulated nanowires are disclosed.
US20140035169 TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION  
A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second...
US20070007670 Reworkable bond pad structure  
A bond pad structure includes a plurality of normal bond pads, a conductive structure and a plurality of backup bond pads. The conductive structure has a plurality of blocks, and at least one of...
US20120241986 Pin Routing in Standard Cells  
Cells designed to accommodate metal routing tracks having a pitch that is an odd multiple of a manufacturing grid. The cells includes cell pins that are located within the cell based on the...
US20070045871 Pad open structure  
A pad open structure, after an insulation layer is installed at the up of the pad, the insulation layer forms plural pad opens by lithography. The insulation layer is exposed to the surface of the...
US20110233753 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: forming a paddle, an inner post adjacent to the paddle, a jumper pad, and an outer post, with the jumper pad between the...
US20120112352 INTEGRATED CIRCUIT SYSTEM WITH DISTRIBUTED POWER SUPPLY  
An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The...
US20050275096 Pre-doped reflow interconnections for copper pads  
A metal interconnect structure (100) comprising a bond pad (110) of copper; a body (103) of eutectic alloy in contact with the bond pad, this alloy including copper; and a contact pad (120)...
US20080093749 Partial Solder Mask Defined Pad Design  
A solder ball pad that includes a substrate and a bonding pad attached to the substrate. The bonding pad has a bonding pad surface and a bonding pad edge. The solder ball pad also includes a...
US20110084365 Through Silicon Via (TSV) Wire Bond Architecture  
A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top...
US20150001740 SOLUTION TO DEAL WITH DIE WARPAGE DURING 3D DIE-TO-DIE STACKING  
A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein...
US20120181707 Distributed Metal Routing  
A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate...
US20110042824 MULTI-CHIP MODULE AND METHOD OF MANUFACTURING THE SAME  
A multi-chip module includes a package board, a plurality of chips, and a wiring board. The plurality of chips are horizontally disposed on the package board. The plurality of chips are...
US20070290373 Multilayer bonding ribbon  
A bonding wire takes the form of a ribbon, and a bond includes such a bonding wire. The bonding wire includes at least two layers having different current carrying capacity.
US20140353849 SYSTEM FOR PREVENTING TAMPERING WITH INTEGRATED CIRCUIT  
A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the...
US20050194698 Integrated circuit package with keep-out zone overlapping undercut zone  
An integrated circuit package is provided with a connective structure having a wire bonding zone and a keep-out zone. An integrated circuit die has an undercut defining an undercut zone, which is...
US20060170114 Novel method for copper wafer wire bonding  
A method of bonding a conductive wire on copper pad is presented. A passivation layer is formed on a copper pad. The passivation layer has an opening through which at least a portion of the copper...
US20070222086 On-die bond wires system and method for enhancing routability of a redistribution layer  
An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads....
US20110018144 WIRING BOARD AND SEMICONDUCTOR DEVICE  
A wiring board includes a core substrate including an insulation base member; linear conductors configured to pierce from a first surface of the insulation base member to a second surface of the...
US20070044057 Semiconductor device with multiple wiring layers and moisture-protective ring  
A semiconductor device with a space-saving design of common power lines shared by a plurality of function macros. An LSI chip has a plurality of wiring layers, a moisture-protective ring, and a...
US20140048935 INTEGRATED CIRCUIT DEVICE  
An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit and a...
US20070035036 Semiconductor device, laminated semiconductor device, and wiring substrate  
The semiconductor device according to the present invention includes a semiconductor chip and a wiring substrate on which a wiring pattern is formed. The wiring pattern includes wire bond...
US20120018905 ELECTRONIC COMPONENT ASSEMBLY HAVING PROFILED ENCAPSULATED BONDS  
An electronic component assembly is provided having an integrated circuit supported on a first mounting area such that a first surface of the integrated circuit contacts the first mounting area,...
US20120211902 BOND PAD STRUCTURE  
A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive...
US20080191367 SEMICONDUCTOR PACKAGE WIRE BONDING  
A stacked die semiconductor package comprises a die coupled to a substrate, the first die having a die bonding area, a bonding wire supporting layer affixed to a top surface of the first die, and...
US20110049671 BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT CHIP USING SUCH BONDING PAD STRUCTURE  
An integrated circuit chip includes a substrate; a topmost metal layer over the substrate; a lower metal layer on or over the substrate and lower than the topmost metal layer; and at least one...
US20120133057 EDGE CONNECT WAFER LEVEL STACKING  
A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at...
US20110187007 EDGE CONNECT WAFER LEVEL STACKING  
A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at...
US20140319703 SELF-DEFINING, LOW CAPACITANCE WIRE BOND PAD  
A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining...
US20120032354 WIREBONDING METHOD AND DEVICE ENABLING HIGH-SPEED REVERSE WEDGE BONDING OF WIRE BONDS  
Methods and systems are described for enabling the efficient fabrication of wedge bonding of integrated circuit systems and electronic systems. In particular a reverse bonding approach can be...
US20130026658 WAFER LEVEL CHIP SCALE PACKAGE FOR WIRE-BONDING CONNECTION  
Primarily disclosed is a wafer-level chip-scale-package (WLCSP) for wire-bonding connection. A first encapsulating layer is formed over a passivation layer of a chip. An RDL (redistribution wiring...
US20090273064 Semiconductor device and inspection method therefor  
A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for...
US20090102065 BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME  
A bonding pad includes an insulation layer with a trench, and a conductive pattern one portion of which is buried into the trench and the other portion of which is formed in a plate shape over the...
US20130264723 METAL BASE SUBSTRATE AND MANUFACTURING METHOD THEREOF  
In a metal base substrate with a low-temperature sintering ceramic layer located on a copper substrate, bonding reliability is increased between the copper substrate and the low-temperature...
US20070273047 PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF  
A printed wiring board having an interlayer insulation layer and conductive circuits formed on the interlayer insulation layer. The conductive circuits include a first conductive circuit and a...
US20100007034 LENS SUPPORT AND WIREBOND PROTECTOR  
A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical...
US20050269718 Optimized driver layout for integrated circuits with staggered bond pads  
One embodiment of a method and system is disclosed. The method configures a plurality of bond pads on a die arranged in a staggered array. The staggered array includes an inner and outer ring of...
US20090108474 JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A junction structure and a method of manufacturing the same are provided which can achieve stable wire bonding between a Poly-Si film bonding pad and an Al wire. The junction structure is made up...
US20150194395 BOND PAD HAVING A TRENCH AND METHOD FOR FORMING  
A method includes forming a conductive bond pad over a conductive structure in a last metal layer of an integrated circuit. A trench is etched around at least a portion of a perimeter of a wire...
US20080197509 Semiconductor package having stacked semiconductor chips  
A semiconductor package including: a package substrate on the surface of which plural connection terminals are provided; a semiconductor chip on the surface of which plural bonding pads are...
US20090146321 WIRE BONDING PERSONALIZATION AND DISCRETE COMPONENT ATTACHMENT ON WIREBOND PADS  
Inner wire bond pads are formed within a peripheral region of a semiconductor chip and at least one bonding wire is attached to the inner wire bond pads. The semiconductor chip may be customized...
US20100025864 SHIELDED WIREBOND  
A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at...
US20100314718 Processes and structures for IC fabrication  
The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the...
US20120068365 METAL CAN IMPEDANCE CONTROL STRUCTURE  
A microelectronic assembly includes an interconnection element, element contacts, first and second metal layers, conductive elements, and first and second microelectronic devices. The first metal...
US20050133897 Stack package with improved heat radiation and module having the stack package mounted thereon  
A stack package with improved heat radiation capability and a module having the stack package mounted thereon are provided in which the back surfaces of first and second chips are exposed through...
US20130193589 PACKAGED INTEGRATED CIRCUIT USING WIRE BONDS  
A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate...
US20110147928 MICROELECTRONIC ASSEMBLY WITH BOND ELEMENTS HAVING LOWERED INDUCTANCE  
Microelectronic assemblies can have multiple conductive bond elements, e.g., bond wires, or a lead bond and a bond wire, extending between a pair of a substrate contact and a chip contact. E.g., a...
US20100244200 Integrated circuit connecting structure having flexible layout  
A wafer has a cutting part filled with a connecting medium. After the wafer is cut into chips along the cutting part, two contacts on two surfaces of the chip can be connected through...
US20090079081 ELECTRONIC DEVICE WITH WIRE BONDS ADHERED BETWEEN INTEGRATED CIRCUITS DIES AND PRINTED CIRCUIT BOARDS  
An electronic device that has an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors corresponding to each of the contact pads...
US20090179336 Electronic Module and a Method of Assembling Such a Module  
The module is of the type comprising an electronic component provided with a conductive face that is electrically connected to a connection member of the component by means of a conductor that is...

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