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US20140252629 Self-Aligned Pitch Split for Unidirectional Metal Wiring  
Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring...
US20150115442 Redistribution layer and method of forming a redistribution layer  
A redistribution layer for a chip is provided, wherein the redistribution layer comprises at least one electrical conductor path connecting two connection points with each other, wherein the at...
US20080296772 Semicondutor device  
A semiconductor device according to the present invention includes: a lower wire having copper as a main component; an insulating film formed on the lower wire; an upper wire formed on the...
US20080251916 UBM structure for strengthening solder bumps  
A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically...
US20060027931 Semiconductor device and method fabricating the same  
A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the...
US20130100185 ALCu HARD MASK PROCESS  
A process for forming a metal interconnection in an integrated circuit includes forming a first metal layer and a second metal layer on the first metal layer. Photoresist is placed on the second...
US20090065842 Ta-lined tungsten plugs for transistor-local hydrogen gathering  
The present electronic device includes a dielectric body having an opening therein. A tantalum layer is provided in the opening of the dielectric body, the layer having the characteristic of...
US20050093155 Barrier layer including a titanium nitride liner for a copper metallization layer including a low-k dielectric  
An improved barrier technology for interconnect features, especially for copper-based interconnects, is provided. A thin titanium nitride liner is conformally deposited by chemical vapor...
US20150228605 Interconnect Structure and Method of Forming the Same  
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the...
US20140167268 GRAPHENE AND METAL INTERCONNECTS  
A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene...
US20100176514 INTERCONNECT WITH RECESSED DIELECTRIC ADJACENT A NOBLE METAL CAP  
The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap.
US20150214177 COATING LAYER FOR A CONDUCTIVE STRUCTURE  
A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer...
US20050179137 Semiconductor device having copper damascene interconnection and fabricating method thereof  
A silicon carbon nitride film is formed on an interlayer dielectric film having Si—H bonds and a Cu interconnection. The silicon carbon nitride film has the role of blocking moisture absorption...
US20090039515 IONIZING RADIATION BLOCKING IN IC CHIP TO REDUCE SOFT ERRORS  
Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip;...
US20120038050 SPUTTERING TARGET  
A sputtering target consists of high purity Nb of which Ta content is 3000 ppm or less and oxygen content is 200 ppm or less. Dispersion of the Ta content in all the sputtering target is within...
US20050056939 Thin-film capacitor and method of producing the capacitor  
A thin-film capacitor comprising a first thin-film electrode, a second thin-film electrode, and a thin dielectric film arranged therebetween and formed of a tantalum oxide layer and an aluminum...
US20120326314 LARGE-GRAIN, LOW-RESISTIVITY TUNGSTEN ON A CONDUCTIVE COMPOUND  
A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing...
US20120228773 LARGE-GRAIN, LOW-RESISTIVITY TUNGSTEN ON A CONDUCTIVE COMPOUND  
A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing...
US20080308942 SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER  
Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring...
US20110108990 Capping of Copper Interconnect Lines in Integrated Circuit Devices  
A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also...
US20110147939 METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS  
A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and...
US20090302475 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a first interlayer insulating film, and a plurality of first interconnects formed in the first interlayer insulating film. A void is selectively formed between...
US20060202345 Barrier layers for conductive features  
Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier...
US20140042630 CONTROLLED COLLAPSE CHIP CONNECTION (C4) STRUCTURE AND METHODS OF FORMING  
Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4)...
US20060001162 Nitride and polysilicon interface with titanium layer  
A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the...
US20130037956 THIN FILM STRUCTURE FOR HIGH DENSITY INDUCTORS AND REDISTRIBUTION IN WAFER LEVEL PACKAGING  
Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact...
US20090134393 THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE  
A thin-film transistor substrate in which an aluminum alloy film composing a source/drain wiring is directly connected with a transparent electrode. The thin-film transistor substrate includes a...
US20150235944 TSV DEEP TRENCH CAPACITOR AND ANTI-FUSE STRUCTURE  
A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an...
US20100025852 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
To suppress deterioration in reliability of wiring and to reduce effective dielectric constant of wiring. In a semiconductor device, copper-containing wirings are covered by barrier insulating...
US20150228607 LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS  
In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder...
US20080079006 SIGNAL LINE FOR A DISPLAY DEVICE, ETCHANT, THIN FILM TRANSISTOR PANEL, AND METHOD FOR MANUFACTURING THE SAME  
A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data...
US20140008804 COPPER INTERCONNECTS SEPARATED BY AIR GAPS AND METHOD OF MAKING THEREOF  
A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device...
US20130020708 Copper Interconnects Separated by Air Gaps and Method of Making Thereof  
A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device...
US20080054470 Semiconductor Device and Method of Fabricating the Same  
The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the...
US20070040275 Semiconductor device including diffusion barrier and method for manufacturing the same  
Provided are a semiconductor device including a diffusion barrier and a method for manufacturing the same. In the method, an interlayer insulating layer on a semiconductor substrate is formed. The...
US20080265423 LAYERED STRUCTURE FOR CORROSION RESISTANT INTERCONNECT CONTACTS  
The present invention is directed to an interconnect for an implantable medical device. The interconnect includes a first conductive layer, a second conductive layer introduced over the first...
US20090146308 NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first...
US20130001786 OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE  
A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first...
US20070138637 Electronic device having low background luminescence, a black layer, or any combination thereof  
An electronic device or a process of forming an electronic device can include a first electrode configured to achieve low Lbackground or include a black layer. An electronic device can include a...
US20080315422 Methods and apparatuses for three dimensional integrated circuits  
Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole...
US20120292773 Method for Producing a Metal Layer on a Substrate and Device  
A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a...
US20090273087 CLOSED-LOOP SPUTTERING CONTROLLED TO ENHANCE ELECTRICAL CHARACTERISTICS IN DEPOSITED LAYER  
This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide...
US20090072406 INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME  
An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect...
US20150221740 METAL SEMICONDUCTOR ALLOY CONTACT RESISTANCE IMPROVEMENT  
Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal...
US20110204520 METAL ELECTRODE AND SEMICONDUCTOR ELEMENT USING THE SAME  
A metal electrode is used for a pair with a semiconductor so as to sandwich a high-dielectric constant thin film between the metal electrode and the semiconductor. A metal electrode 13 comprises a...
US20150171180 SEMICONDUCTOR DEVICE HAVING ELECTRODE MADE OF HIGH WORK FUNCTION MATERIAL, METHOD AND APPARATUS FOR MANUFACTURING THE SAME  
Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation resistance. The semiconductor device...
US20110079908 Stress buffer to protect device features  
Disclosed is a stress buffer structure intended to be disposed adjacent a face of a semiconductor substrate. The stress buffer structure includes at least one polymer layer formed on the face of...
US20150171179 SEMICONDUCTOR DEVICE HAVING ELECTRODE MADE OF HIGH WORK FUNCTION MATERIAL AND METHOD OF MANUFACTURING THE SAME  
Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation resistance. The semiconductor device...
US20100181674 ELECTRICAL CONTACTS FOR CMOS DEVICES AND III-V DEVICES FORMED ON A SILICON SUBSTRATE  
A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the...
US20080054469 Electroformed metal structure  
A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate...

Matches 1 - 50 out of 77 1 2 >