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US20090294994 BOND PAD STRUCTURE  
A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit...
US20090294945 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR  
The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein....
US20090289369 MEMORY DEVICE PERIPHERAL INTERCONNECTS AND METHOD OF MANUFACTURING  
An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the...
US20090283912 DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP ETCH PROCESS WITH HARD MASK RETENTION  
Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first...
US20090283911 Backend Interconnect Scheme with Middle Dielectric Layer Having Improved Strength  
An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal...
US20090273086 METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES  
During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may...
US20090273009 Integrated CMOS porous sensor  
A single chip wireless sensor ( 1 ) comprises a microcontroller ( 2 ) connected by a transmit/receive interface ( 3 ) to a wireless antenna ( 4 ). The microcontroller ( 2 ) is also connected to an...
US20090267233 BONDED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME  
A bonded semiconductor structure static random access memory circuit includes a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a...
US20090267232 METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT  
An integrated circuit ( 100 ) is provided that comprises a substrate ( 140 ) of silicon and an interconnect ( 130 ) in a through-hole extending from the first to the second side of the substrate....
US20090261475 METHOD FOR FABRICATING A METAL INTERCONNECTION USING A DUAL DAMASCENE PROCESS AND RESULTING SEMICONDUCTOR DEVICE  
A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower...
US20090256260 SEMICONDUCTOR DEVICE  
A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture...
US20090250820 CONFIGURABLE NON-VOLATILE LOGIC STRUCTURE FOR CHARACTERIZING AN INTEGRATED CIRCUIT DEVICE  
An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision...
US20090250819 METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME  
The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an...
US20090243110 Voltage controlled oscillator  
A semiconductor device includes a semiconductor substrate having an element region on a surface thereof, an active element being formed in the element region. An insulating layer is formed on the...
US20090243109 METAL CAP LAYER OF INCREASED ELECTRODE POTENTIAL FOR COPPER-BASED METAL REGIONS IN SEMICONDUCTOR DEVICES  
A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained...
US20090243108 CONTROL OF LOCALIZED AIR GAP FORMATION IN AN INTERCONNECT STACK  
The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect...
US20090230556 NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS AND MANUFACTURING METHOD THEREOF  
A nonvolatile semiconductor memory apparatus 25 comprises a semiconductor substrate 11 , a lower-layer wire 12 formed on the semiconductor substrate 11 , an upper-layer wire 20 formed above...
US20090224405 THROUGH VIA PROCESS  
A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a...
US20090224374 ADVANCED MULTILAYER DIELECTRIC CAP WITH IMPROVED MECHANICAL AND ELECTRICAL PROPERTIES  
A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one...
US20090200677 SEMICONDUCTOR DEVICE  
A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip...
US20090200676 SEMICONDUCTOR DEVICE  
A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100...
US20090200675 Passivated Copper Chip Pads  
A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed...
US20090200674 STRUCTURE AND METHOD OF FORMING TRANSITIONAL CONTACTS BETWEEN WIDE AND THIN BEOL WIRINGS  
A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having...
US20090194879 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution...
US20090189285 ON CHIP THERMOCOUPLE AND/OR POWER SUPPLY AND A DESIGN STRUCTURE FOR SAME  
A thermocouple and power supply structure. The structure is interleaved through a substrate. The structure includes a first through via extending through the substrate and connected to a first...
US20090184424 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME  
The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the...
US20090179332 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device including a semiconductor substrate; a first insulating film formed on the semiconductor substrate including a contact hole opened therethrough; a lower plug filled in the...
US20090166873 INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME  
The interconnecting structure for a semiconductor die includes a die having bonding pads on an active surface; a core attached the side wall (edge) of the die by adhesion material; an isolating...
US20090160058 Structure and process for the formation of TSVs  
An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal...
US20090152728 SEMICONDUCTOR APPARATUS  
A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a...
US20090146129 MULTI-BIT MEMORY CELL STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A method of manufacturing a semiconductor memory cell including phase change material. A multi-bit memory cell may implement phase change material. Various kinds of information can be stored in one...
US20090140431 HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE  
By forming the first metallization layer of a semiconductor device as a dual damascene structure, the contact elements may be formed on the basis of a significantly reduced aspect ratio, thereby...
US20090127711 INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME  
A highly reliable copper interconnect structure and method of fabricating the same is provided. The interconnect structure comprises a metal layer buried between an adjacent upper copper layer and...
US20090127709 SEMICONDUCTOR DEVICE  
A semiconductor device according to the present invention includes: a semiconductor chip; a wiring formed on the semiconductor chip; a passivation film, coating the wiring and having an opening for...
US20090121359 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24 ) formed on the semiconductor substrate, having a first trench (second interconnect...
US20090121357 DESIGN STRUCTURE FOR BRIDGE OF A SEMINCONDUCTOR INTERNAL NODE  
A design structure for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The...
US20090108454 METAL LINE IN SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF  
A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact...
US20090108453 CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME  
A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first...
US20090096104 Semiconductor device having crack stop structure  
Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor...
US20090091035 Highly integrated and reliable DRAM and its manufacture  
A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon...
US20090085214 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a...
US20090039451 METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE  
A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer...
US20090032955 SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD AND DISPLAY APPARATUS  
A semiconductor device including n, where notation n denotes a positive integer at least equal to three, conductive layers created as stacked layers on a substrate and connected to each other...
US20090026620 METHOD FOR CUTTING MULTILAYER SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE, AND BACKLIGHT DEVICE  
In order to cut off, without causing any burr, a multilayer substrate having a metal layer on a front surface and a second metal layer on a back surface, a method for cutting the multilayer...
US20090014881 SEMICONDUCTOR DEVICE, AND METHOD AND APPARATUS FOR MANUFACTURING SAME  
For the purpose of removing an oxide film on the surface of a varying metal electroconductive material used for wiring in a semiconductor device without inflicting damage on a peripheral structure,...
US20090001590 WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first...
US20090001589 NOR FLASH DEVICE AND METHOD FOR FABRICATING THE DEVICE  
An NOR flash memory device having a back end of line (BEOL) structure, the BEOL structure including a substrate having a conductive region, a first intermetal dielectric layer formed on the...
US20080315421 Die backside metallization and surface activated bonding for stacked die packages  
Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be...
US20080315420 Metal pad formation method and metal pad structure using the same  
A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A...
US20080308940 LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES  
A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first...
Matches 1 - 50 out of 127 1 2 3 >