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US20090102036 Stacked semiconductor package having interposing print circuit board  
A stacked semiconductor package including a number of solder ball pads formed on a lower surface of an interposing print circuit board, which is smaller than that of solder ball pads formed on an...
US20090096077 Tenon-and-mortise packaging structure  
A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least...
US20070152316 Interposer pattern with pad chain  
Provided is an interposer pattern having a conductive material for forming a pad chain that can reduce a wafer test time. The interposer pattern includes one or more interposers and an external...
US20150130040 High Density Microelectronics Packaging  
Example packaging of microelectronics and example methods of manufacturing the same are provided herein. The packaging can enable and/or improve the use of the microelectronics in a downhole, high...
US20100072602 STACKED INTEGRATED CIRCUIT PACKAGE USING A WINDOW SUBSTRATE  
An integrated circuit (IC) package is disclosed. The IC package includes a first substrate having a first surface having first substrate bond pads, a second surface having second substrate bond...
US20110108973 CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME  
The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress...
US20060249829 Stacked type semiconductor device  
A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the...
US20110042795 Three-Dimensional Silicon Interposer for Low Voltage Low Power Systems  
Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of...
US20110147907 ACTIVE PLASTIC BRIDGE CHIPS  
A system for proximity communication between semiconductor chips includes a package assembly. The package assembly includes a plurality of bridge circuits made of organic or plastic semiconductor...
US20110215457 Dummy TSV to Improve Process Uniformity and Heat Dissipation  
In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning,...
US20100314738 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACK PACKAGE AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing a stack board; connecting a device over the stack board; forming a stack encapsulant having a cavity and a...
US20110037159 Electrically Interconnected Stacked Die Assemblies  
In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some...
US20090020863 Stacked semiconductor devices and signal distribution methods thereof  
A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal...
US20050205981 Stacked electronic part  
A stacked electronic part comprises a first electronic part which is adhered onto a circuit board via a first adhesive layer and a second electronic part which is adhered onto the first electronic...
US20090152702 Coupling wire to semiconductor region  
A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the...
US20080105961 Ligands of the Molecule Fit (Agt-121) and their Pharmaceutical Use  
Identification of molecules which modulate inter alia obesity, anorexia, weight maintenance, inflammation and/or metabolic energy levels in a subject are described which particularly relate to a...
US20110147906 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated...
US20070132082 Copper plating connection for multi-die stack in substrate package  
An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another...
US20090273068 3-D Integrated Circuit Lateral Heat Dissipation  
By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The...
US20090001540 Stackable Package by Using Internal Stacking Modules  
A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical...
US20110175215 3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP  
A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including...
US20090067135 Semiconductor Package Having Socket Function, Semiconductor Module, Electronic Circuit Module and Circuit Board with Socket  
Disclosed is a semiconductor package 3 including a socket 1 which is formed on the top surface 3a for enabling electrical conductivity and a connecting terminal 2 which is formed on the bottom...
US20080169547 SEMICONDUCTOR MODULES WITH ENHANCED JOINT RELIABILITY  
Provided is a semiconductor module with enhanced joint reliability. The semiconductor module includes a package, a printed circuit board (PCB), and conductive joint structures for electrically...
US20080093723 Passive placement in wire-bonded microelectronics  
A microelectronic assembly includes a first microelectronic device electrically coupled with a second microelectronic device via wire bond attachment, the first microelectronic device being...
US20100059872 Adhesive Tape, Connected Structure and Semiconductor Package  
An adhesive tape 101 electrically connecting conductive components includes a resin layer 132 containing a thermosetting resin, a solder powder 103 and a curing agent. The solder powder 103 and...
US20080303131 ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES  
In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some...
US20090267210 INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF  
An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding...
US20070052084 High density interconnect assembly comprising stacked electronic module  
A microelectronic module is provided with one or more first conductive pads on at least one of the exterior surfaces of the module for electrical interconnection of the functionality of the module...
US20080128880 DIE STACKING USING INSULATED WIRE BONDS  
A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low...
US20070013041 Flexible wiring board and flex-rigid wiring board  
The invention provides a flexible wiring board for repeated folding sections which exhibits excellent folding endurance, and a flex-rigid wiring board comprising the flexible wiring board as a...
US20080017966 Pillar Bump Package Technology  
A semiconductor product includes a die and leadframe included in a package made of plastic or other insulating material. The die and leadframe are dimensioned so that they overlap in at least one...
US20110012249 IC CHIP PACKAGE HAVING IC CHIP WITH OVERHANG AND/OR BGA BLOCKING UNDERFILL MATERIAL FLOW AND RELATED METHODS  
An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall...
US20080054437 POP PACKAGE AND METHOD OF FABRICATING THE SAME  
A package-on-package (POP) package in which semiconductor packages are stacked using lead lines rather than conventional solder balls, and a fabricating method thereof are provided. According to...
US20050133897 Stack package with improved heat radiation and module having the stack package mounted thereon  
A stack package with improved heat radiation capability and a module having the stack package mounted thereon are provided in which the back surfaces of first and second chips are exposed through...
US20100187670 On-Chip Heat Spreader  
A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first...
US20060060955 Stacked die infrared transceiver bus  
A semiconductor stacked die package adapted to wirelessly transfer data between stacked dies. The package comprises a plurality of dies, each die adjacent another die and each die comprising an...
US20070158812 Method of testing wires and apparatus for doing the same  
In a substrate including a plurality of first wires to be tested, and a plurality of second wires each defining a capacity with each of the first wires, a method of testing whether said first...
US20070057357 System in package (SIP) structure  
A System In Package (SIP) arrangement and method of connecting a plurality of flip chips and wire bond chips with reduced wiring complexity and increase flexibility. The SIP arrangement includes...
US20110024889 PACKAGE ARCHITECTURE  
A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated...
US20100224975 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL BOARD-ON-CHIP STRUCTURE AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the...
US20090189266 SEMICONDUCTOR PACKAGE WITH STACKED DICE FOR A BUCK CONVERTER  
Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one...
US20080251906 Package-on-package secure module having BGA mesh cap  
A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a...
US20100032821 TRIPLE TIER PACKAGE ON PACKAGE SYSTEM  
An integrated circuit package system includes: providing a first package having a first interposer mounted over a first integrated circuit and the first integrated circuit encapsulated by a first...
US20080083977 Edge connect wafer level stacking  
In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly...
US20080093725 SEMICONDUCTOR PACKAGE PREVENTING WARPING AND WIRE SEVERING DEFECTS, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE  
Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a circuit substrate having a slit inside the circuit substrate, a semiconductor chip...
US20090236726 PACKAGE-ON-PACKAGE SEMICONDUCTOR STRUCTURE  
A semiconductor package that includes a substrate having first and second major surfaces is presented. The package includes a plurality of landing pads and a semiconductor die disposed on the...
US20070096285 Semiconductor die package including construction for preventing delamination and/or cracking of the semiconductor die  
A semiconductor die substrate is disclosed for preventing delamination of the die and/or die cracking due to air bubbles trapped beneath the die, and a semiconductor package incorporating the...
US20080023813 Multi-die apparatus including moveable portions  
An electronic apparatus includes a first die, a second die, a third die, and a fourth die, wherein a portion of the second die and a portion of the third die are movably connected between the...
US20060076690 Stacked Die Module  
Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same...
US20080179729 ENCAPSULANT CAVITY INTEGRATED CIRCUIT PACKAGE SYSTEM  
An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and...