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US20110127648 Heat Spreader Structures in Scribe Lines  
An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge...
US20140077341 INTEGRATED CIRCUIT AND SEAL RING  
An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger...
US20130075869 Chip Comprising a Fill Structure  
A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.
US20150255405 CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP  
A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the...
US20090321889 Scribe Seal Connection  
A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical impurities introduced during...
US20110278701 Scribe line structure for wafer dicing  
The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one...
US20140167225 Crack Stop Barrier and Method of Manufacturing Thereof  
A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier.
US20150061081 CRACK DEFLECTOR STRUCTURE FOR IMPROVING SEMICONDUCTOR DEVICE ROBUSTNESS AGAINST SAW-INDUCED DAMAGE  
An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a...
US20120181669 FRAME CELL FOR SHOT LAYOUT FLEXIBILITY  
A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least...
US20150097271 SELF-HEALING CRACK STOP STRUCTURE  
A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an...
US20150001683 DICE BEFORE GRIND WITH BACKSIDE METAL  
A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the...
US20130207239 Interconnect Crack Arrestor Structure and Methods  
A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in...
US20080246031 PCM pad design for peeling prevention  
A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe...
US20100123219 Heat Spreader Structures in Scribe Lines  
An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge...
US20090194850 Crack Stops for Semiconductor Devices  
Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device...
US20090051010 IC package sacrificial structures for crack propagation confinement  
Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive...
US20140167226 Wafer and a Method of Dicing a Wafer  
A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
US20120161294 Method of Batch Trimming Circuit Elements  
Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose...
US20090057842 SELECTIVE REMOVAL OF ON-DIE REDISTRIBUTION INTERCONNECTS FROM SCRIBE-LINES  
Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a...
US20150040983 ACIDIC ETCHING PROCESS FOR SI WAFERS  
The present invention relates to a method for acidic surface etching of a silicon wafer, such as those used for solar cells, comprising contacting at least one surface of a silicon wafer as cut...
US20080157286 Semiconductor device having a indicator indicating cleavage direction  
An indicator that denotes the cleavage direction is arranged along with an integrated circuit of a semiconductor chip. This indicator makes it possible to cut the semiconductor chip along the...
US20120162622 FIELD EXTENSION TO REDUCE NON-YIELDING EXPOSURES OF WAFER  
Techniques are provided for efficient lithography processing and wafer layout. In particular, the techniques can be used to reduce the number of sacrificial exposures along the wafer perimeter...
US20060012012 Semiconductor device with crack prevention ring and method of manufacture thereof  
A method of forming a crack prevention ring at the exterior edge of an integrated circuit to prevent delamination and cracking during the separation of the integrated circuits into individual die....
US20050263854 Thick laser-scribed GaN-on-sapphire optoelectronic devices  
A sapphire wafer having a thickness greater than 125 microns and having devices disposed thereon is laser scribed to form a grid array pattern of laser scribe lines laser scribed into the sapphire...
US20100013059 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES  
The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first...
US20140035107 DOUBLE SEAL RING  
A double seal ring for an integrated circuit, the double seal ring includes a first seal ring surrounding the integrated circuit and a second seal ring spaced from the first seal ring. The double...
US20150076665 ALIGNMENT MARK STRUCTURE  
A conductive structure includes a wafer having a scribe line defined thereon, at least a first wiring layer formed in the scribe line, and at least a via layer disposed in the scribe line and...
US20060278956 Semiconductor wafer with non-rectangular shaped dice  
A semiconductor wafer having a plurality of dice formed on the wafer. The plurality of dice having non-rectangular shapes with at least one notched corner. A plurality of saw streets are defined...
US20130027073 INTEGRATED CIRCUIT COMPRISING AT LEAST AN INTEGRATED ANTENNA  
An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other...
US20130299947 PASSIVATED TEST STRUCTURES TO ENABLE SAW SINGULATION OF WAFER  
A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test...
US20140054750 Scribe line structure for wafer dicing and method of making the same  
A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in...
US20110127644 WAFER AND METHOD FOR FORMING THE SAME  
A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer...
US20120250429 SECURITY-PROTECTION OF A WAFER OF ELECTRONIC CIRCUITS  
A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing...
US20110147897 OFFSET FIELD GRID FOR EFFICIENT WAFER LAYOUT  
Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on...
US20110127646 WAFER AND METHOD FOR FORMING THE SAME  
A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer...
US20120098104 SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT  
Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of...
US20140339558 ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY  
Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first...
US20130154062 Die Structure and Method of Fabrication Thereof  
A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a...
US20080203538 Semiconductor wafer with division guide pattern  
A plurality of semiconductor elements and division regions are provided on a semiconductor subsubstrate. A modification region is provided in the semiconductor substrate. A division guide pattern...
US20140264767 Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip  
A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench...
US20100207251 Scribe Line Metal Structure  
A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a...
US20110127645 WAFER AND METHOD FOR FORMING THE SAME  
A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer...
US20070102792 MULTI-LAYER CRACK STOP STRUCTURE  
A multi-layer crack stop structure is described, disposed entirely in a die, entirely in a scribe line region outside the die, or partially in the die and partially in the scribe line region. The...
US20140312466 INTEGRATED CIRCUIT SEALING SYSTEM WITH BROKEN SEAL RING  
The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating a wide seal ring...
US20080099884 Staggered guard ring structure  
Embodiments of the present invention provide staggered guard ring structures for stopping cracks from propagating during a dicing operation or by suffering mechanical stress after packaging. In...
US20100244200 Integrated circuit connecting structure having flexible layout  
A wafer has a cutting part filled with a connecting medium. After the wafer is cut into chips along the cutting part, two contacts on two surfaces of the chip can be connected through...
US20100090316 WAFER WITH DESIGN PRINTED THEREIN  
A printed wafer. A design is printed within a peripheral portion of the wafer. The peripheral portion of the wafer is between an outer boundary of an active portion of the wafer and an outer...
US20140103496 SEAL RING STRUCTURES WITH REDUCED MOISTURE-INDUCED RELIABILITY DEGRADATION  
A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first...
US20090039470 STRESS RELIEF OF A SEMICONDUCTOR DEVICE  
A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment,...
US20110068436 METHODS AND STRUCTURES FOR ENHANCING PERIMETER-TO-SURFACE AREA HOMOGENEITY  
Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate...

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