Matches 151 - 200 out of 422 < 1 2 3 4 5 6 7 8 9 >


Match Document Document Title
US20120098105 BOND PAD FOR WAFER AND PACKAGE FOR CMOS IMAGER  
An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal...
US20090146260 Semiconductor wafer including cracking stopper structure and method of forming the same  
A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend...
US20080012096 SEMICONDUCTOR CHIP AND METHOD OF FORMING THE SAME  
A semiconductor chip and method of forming the same are described. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and a rim side connecting the...
US20140117505 Chip Having Backside Metal and Method for Manufacturing Same  
A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are...
US20140346644 Exclusion Zone for Stress-Sensitive Circuit Design  
A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are...
US20130328172 WAFER-LEVEL FLIP CHIP DEVICE PACKAGES AND RELATED METHODS  
In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical...
US20090294912 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor...
US20110140245 STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES  
A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter....
US20090051011 Semiconductor device having seal ring structure and method of forming the same  
A semiconductor device of the present invention includes a seal ring structure. The seal ring structure includes a first metal layer including a though hole, the through hole having a bottom...
US20100096729 GEOMETRY AND DESIGN FOR CONFORMAL ELECTRONICS  
A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to...
US20090321891 METHOD AND APPARATUS FOR GENERATING RETICLE DATA  
A method for generating reticle data for forming a reticle. The method includes recognizing a non-layout region free from main chips in a process pattern, dividing the non-layout region into a...
US20090091001 CRACK RESISTANT SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME  
There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a...
US20100176493 METHOD OF SPLITTING A SUBSTRATE  
A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate...
US20130334668 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: forming an integrated circuit device having a device contact surface, a device lateral side, and a device backside...
US20110241179 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES  
The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first...
US20050006726 Apparatus and method for testing semiconductor nodules on a semiconductor substrate wafer  
A method and an apparatus for testing semiconductor modules of a semiconductor substrate wafer are proposed, which can be used to increase a test economy. This is achieved by the semiconductor...
US20140264771 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF  
An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined...
US20140252560 SUBMOUNT ASSEMBLY INTEGRATION  
In accordance with one embodiment, an apparatus is disclosed that comprises a submount operable to integrate with a laser as a laser submount assembly; a predetermined portion of the submount...
US20130207240 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF  
An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined...
US20120313222 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF  
An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined...
US20120091565 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME  
A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region...
US20150001684 ELECTROPLATING USING DIELECTRIC BRIDGES  
Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a...
US20140035108 SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME  
A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts...
US20130134559 Chip-on-Wafer Structures and Methods for Forming the Same  
A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature...
US20110248387 SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME  
A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts...
US20090302427 Semiconductor Chip with Reinforcement Structure  
Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip...
US20060163698 Method and apparatus for wafer to wafer bonding  
Inter-wafer structures are formed using semiconductor fabrication methods so as to provide precise, uniform distance between die on a bottom wafer and die on a top wafer. An inter-wafer structure...
US20080258266 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the...
US20080191318 SEMICONDUCTOR DEVICE AND METHOD OF SAWING SEMICONDUCTOR DEVICE  
A method is disclosed for singulating die containing semiconductor device whereby a trench is etched at a first scribe region of a wafer comprising semiconductor devices, and sawing the wafer...
US20080179711 SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE SAME  
According to the present invention, a plurality of semiconductor devices having semiconductor chips 13 molded on a semiconductor package substrate 1 by a molding resin 15 can be manufactured by...
US20120241914 REDUCTION OF FLUORINE CONTAMINATION OF BOND PADS OF SEMICONDUCTOR DEVICES  
A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by...
US20080042245 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER  
An integrated circuit packaging system is provided including forming a first device wafer having a first backside and a first active side; forming a waferscale spacer wafer having a waferscale...
US20150255417 FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING  
A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding...
US20150155263 FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING  
A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding...
US20090121322 Semiconductor chip and semiconductor device  
A semiconductor chip comprises a semiconductor substrate, a multi-layer wiring structure on the semiconductor substrate, a seal ring structure on the semiconductor substrate, and a semiconductor...
US20080230874 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE  
A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer...
US20120299159 STRUCTURE DESIGNS AND METHODS FOR INTEGRATED CIRCUIT ALIGNMENT  
Devices and methods for pattern alignment are disclosed. In one embodiment, a semiconductor device includes a die including an integrated circuit region, an assembly isolation region around the...
US20060091534 Chip part manufacturing method and chip parts  
The present invention provides a chip part manufacturing method comprising a separating process capable of suppressing deformation of chip parts, and also provides chip parts. It comprises a step...
US20080012095 INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WAFER LEVEL SPACER  
An integrated circuit package system that includes providing a wafer level spacer including apertures, which define unit spacers that are interconnected, and configuring the unit spacers to...
US20140346642 SURFACE MOUNTABLE ELECTRONIC COMPONENT  
A surface mountable electronic component free of connecting wires comprises a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the underside of the...
US20110156217 POWER DEVICES HAVING REDUCED ON-RESISTANCE AND METHODS OF THEIR MANUFACTURE  
A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a...
US20150108613 SEMICONDUCTOR CHIP WITH SEAL RING AND SACRIFICIAL CORNER PATTERN  
A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls...
US20060003234 Die identification systems and methods  
Systems and methods are disclosed herein to provide die identification. For example, in accordance with an embodiment of the present invention, a wafer patterning technique is disclosed that...
US20150069578 COMBINATION GRINDING AFTER LASER (GAL) AND LASER ON-OFF FUNCTION TO INCREASE DIE STRENGTH  
Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method...
US20080157285 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the...
US20150061080 GUARD RING STRUCTURE OF SEMICONDUCTOR APPARATUS  
A guard ring structure of a semiconductor apparatus includes a base wiring layer located above a semiconductor substrate, a first guard ring configured as a wiring stacked structure of two or more...
US20120292744 CHIP PACKAGE, METHOD FOR FORMING THE SAME, AND PACKAGE WAFER  
An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer...
US20120038028 MULTIPLE SEAL RING STRUCTURE  
The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring...
US20070205490 Method for Production of Semiconductor Chip, and Semiconductor Chip  
A method for the production of gallium nitride compound semiconductor chips from a wafer having gallium nitride compound semiconductor layers (2, 3) laminated on the principal surface of a...
US20130277806 LASER SUBMOUNTS FORMED USING ETCHING PROCESS  
A wafer is formed having a plurality of laser-to-slider submount features on a first surface. An etching process is used to form scribe lines between the submounts on the first surface of the...

Matches 151 - 200 out of 422 < 1 2 3 4 5 6 7 8 9 >