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US20090152683 ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THERMO-MECHANICAL RELIABILITY  
One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the...
US20090134495 Method of designing semiconductor device  
A design method of a semiconductor device comprising forming a base wafer by using a plurality of semiconductor chips including a plurality of functional macros, generating macro test information...
US20080265378 Scribe line layout design  
A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the...
US20090115024 Seal ring structure with improved cracking protection and reduced problems  
An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the...
US20050212090 Integrated circuit  
An integrated circuit includes a cuttable circuit structure, which in a cut state prevents access to at least one circuit element of the integrated circuit. Whereby, the circuit structure is...
US20140327115 MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS  
A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings...
US20140035106 MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS  
A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings...
US20140103495 WAFER AND METHOD FOR PROCESSING A WAFER  
A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to...
US20150200167 METHODS OF MANAGING METAL DENSITY IN DICING CHANNEL AND RELATED INTEGRATED CIRCUIT STRUCTURES  
Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer...
US20140084425 PERIMETER TRENCH SENSOR ARRAY PACKAGE  
One embodiment of a perimeter trench sensor array package can include a thinned substrate device that includes a perimeter trench formed near the edges of the device that can be configured to be...
US20100109128 Crack Deflector Structure for Improving Semiconductor Device Robustness Against Saw-Induced Damage  
An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a...
US20080122038 GUARD RING STRUCTURE WITH METALLIC MATERIALS  
A semiconductor device and a method for making the semiconductor device having a guard ring formed by a trench filled with a metallic material is described. Using the trench, crack and moisture...
US20150171027 HIGH YIELD SUBSTRATE ASSEMBLY  
High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback...
US20090321890 Protective Seal Ring for Preventing Die-Saw Induced Stress  
A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric...
US20120313223 METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITHOUT GROUND CONTACT PAD  
The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of...
US20070108557 INTEGRATED CIRCUIT SYSTEM WITH WAFER TRIMMING  
An integrated circuit system includes an integrated circuit wafer, forming a trimmed edge on the integrated circuit wafer, and applying a thinning process on the integrated circuit wafer with the...
US20060055002 Methods for enhancing die saw and packaging reliability  
A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench...
US20120153358 INTEGRATED HEAT PILLAR FOR HOT REGION COOLING IN AN INTEGRATED CIRCUIT  
The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit...
US20130043470 CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME  
The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The...
US20080073753 Test line placement to improve die sawing quality  
A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the...
US20120267765 WAFER-LEVELED CHIP PACKAGING STRUCTURE AND METHOD THEREOF  
A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a...
US20100193918 EMBEDDED SCRIBE LANE CRACK ARREST STRUCTURE FOR IMPROVED IC PACKAGE RELIABILITY OF PLASTIC FLIP CHIP DEVICES  
A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality...
US20050110118 Scribe seal providing enhanced substrate noise isolation  
Multiple scribe seals are provided around an integrated circuit on a die to attain enhanced substrate noise isolation. In one embodiment, an inner scribe seal prevents mobile ions from entering...
US20090166810 Semiconductor Device Crack-Deflecting Structure and Method  
The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the...
US20140015114 ELECTRONIC DEVICE MANUFACTURING METHOD, ELECTRONIC DEVICE, AND CHIP ASSEMBLY  
An electronic device manufacturing method includes a cutting step at which a wafer is cut to obtain chips before pattern formation and a polishing step at which cut surfaces of the obtained chips...
US20070029641 Semiconductor device  
A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal...
US20080272465 Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die  
A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by...
US20140264768 Die Preparation for Wafer-Level Chip Scale Package (WLCSP)  
Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the...
US20130292803 CHIP STRUCTURE AND WAFER STRUCTURE  
A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the...
US20100044838 SEMICONDUCTOR COMPONENT WITH MARGINAL REGION  
A semiconductor component having a semiconductor body includes an active region and a marginal region surrounding the active region. The marginal region extends from the active region as far as an...
US20100258916 THERMAL STRESS REDUCTION  
The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes...
US20080023802 SEMICONDUCTOR DEVICE HAVING A SCRIBELINE STRUCTURE FAVORABLE FOR PREVENTING CHIPPING  
A semiconductor device includes at least one semiconductor chip formed on a wafer and a scribeline provided along an outer circumference of the semiconductor chip. The semiconductor device further...
US20150235969 BACKSIDE METALLIZATION PATTERNS FOR INTEGRATED CIRCUITS  
A semiconductor wafer having multiple dies has a partially metallized backside. After wafer dicing, each of the multiple dies has, on its backside, a metallized area surrounded by a peripheral...
US20140175613 Chip Positioning in Multi-Chip Package  
Embodiments of the present invention include a substrate package, a method for multi chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference...
US20110115058 DEVICES WITH CRACK STOPS  
An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a...
US20100078769 ENVIRONMENTAL DIE SEAL ENHANCEMENT FOR WAFER LEVEL CHIP SCALE PACKAGES  
In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional circuit area that does not extend all...
US20060278958 Semiconductor arrangement and method for producing a semiconductor arrangement  
A semiconductor arrangement having at least one semiconductor chip, which has, on one surface, an integrated circuit and at least one contact element which is electrically conductively connected...
US20140084427 MULTI-CORE DIES PRODUCED BY RETICLE SET MODIFICATION  
A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many...
US20120119333 PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP  
Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to...
US20060051936 Mask and production method therefor and production for semiconductor device  
A highly durable mask with sufficient strength against ion implantation, a method of producing the same, and a method of producing a semiconductor device using the mask are provided. A mask...
US20100078768 Wafer cutting methods and packages using dice derived therefrom  
A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes...
US20090272973 Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line  
The present invention discloses a semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of plural semiconductor chips. The semiconductor wafer includes a...
US20120228744 WAFER AND METHOD OF MANUFACTURING PACKAGE PRODUCT  
To provide a wafer in which out-gas emitted between wafers during bonding of the wafers can be easily discharged to the outside and the bonded wafers can be favorably cut to improve the yields,...
US20050082643 Semiconductor element, semiconductor device, method for manufacturing semiconductor element, method for manufacturing semiconductor device, and electronic apparatus  
To provide semiconductor elements, semiconductor devices, methods for manufacturing semiconductor elements, methods for manufacturing semiconductor devices, and electronic apparatuses, when...
US20110115057 DESIGN STRUCTURE FOR INTEGRATED CIRCUIT ALIGNMENT  
A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal...
US20080083922 RADIO FREQUENCY TEST KEY STRUCTURE  
A radio frequency test key structure comprises a substrate, a bottom metal layer and a top metal layer. A narrow testing region is defined on the substrate. The bottom metal layer is positioned on...
US20090140393 WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY  
A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip...
US20110073996 MULTIPLE DIE LAYOUT FOR FACILITATING THE COMBINING OF AN INDIVIDUAL DIE INTO A SINGLE DIE  
A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on...
US20050062135 Semiconductor device and method for fabricating the same  
A semiconductor device and manufacturing method are provided in which chippings are reduced even if they occur during dicing. At least edge portions of a chip and another surface are chamfered to...
US20140217557 Method and Apparatus for a Seal Ring Structure  
A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to...

Matches 51 - 100 out of 422 < 1 2 3 4 5 6 7 8 9 >