Match Document Document Title
US20150130026 PRINTING MINIMUM WIDTH FEATURES AT NON-MINIMUM PITCH AND RESULTING DEVICE  
Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed....
US20130200497 MULTI-LAYER METAL SUPPORT  
The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some...
US20130200496 MULTI-LAYER METAL SUPPORT  
The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some...
US20130043564 ATTACHING A MEMS TO A BONDING WAFER  
A MEMS is attached to a bonding wafer in part by forming a support layer over the MEMS. A first eutectic layer is formed over the support layer. The eutectic layer is patterned into segments to...
US20150076663 Patterned Bases, and Patterning Methods  
Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing...
US20140091434 Patterned Bases, and Patterning Methods  
Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing...
US20120286377 Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof  
Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from...
US20120193762 REVERSAL LITHOGRAPHY APPROACH BY SELECTIVE DEPOSITION OF NANOPARTICLES  
A novel reversal lithography process without etch back is described. The reversal material comprises nanoparticles that are selectively deposited into the gaps between features without overcoating...
US20110012236 EVALUATION OF AN UNDERCUT OF DEEP TRENCH STRUCTURES IN SOI WAFERS  
A technique is provided which enables quantitative evaluation of an undercutting of deep trench structures in semiconductor wafers and, in particular, SOI wafers, by means of electrical or optical...
US20110024879 METHOD TO REDUCE PRE-ALIGNMENT ERROR USING MULTI-NOTCH PATTERN OR IN COMBINATION WITH FLAT SIDE  
A semiconductor wafer has a pre-alignment pattern including two or more notches on the wafer edge and the notches are used for wafer pre-alignment in fabrication processes. In one embodiment, at...
US20120038027 METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE  
The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and...
US20130335109 METHOD OF TEST PROBE ALIGNMENT CONTROL  
A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment...
US20110227200 ALIGNMENT STRUCTURES FOR INTEGRATED-CIRCUIT PACKAGING  
A multi-chip module (MCM) that includes alignment features is described. This MCM includes at least two substrates having facing surfaces with positive features disposed on them. Note that a given...
US20150021743 UNIFORM ROUGHNESS ON BACKSIDE OF A WAFER  
Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes...
US20140117503 EPHEMERAL BONDING  
Compositions suitable for temporarily bonding two surfaces, such as a wafer active side and a substrate, are disclosed. Methods of temporarily bonding two surfaces, such as the active side of a...
US20150001681 Bonded Wafer Edge Protection Scheme  
A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.
US20150170905 METHODS FOR DEVICE FABRICATION USING PITCH REDUCTION AND RELATED DEVICES  
Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied...
US20140299969 HIGHLY ETCH-RESISTANT POLYMER BLOCK FOR USE IN BLOCK COPOLYMERS FOR DIRECTED SELF-ASSEMBLY  
Compositions for directed self-assembly (DSA) patterning techniques are provided. Methods for directed self-assembly are also provided in which a DSA composition comprising a block copolymer is...
US20140191372 SPACER ASSISTED PITCH DIVISION LITHOGRAPHY  
Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting...
US20110284995 MICROMECHANICAL MEMBRANES AND RELATED STRUCTURES AND METHODS  
Micromechanical membranes suitable for formation of mechanical resonating structures are described, as well as methods for making such membranes. The membranes may be formed by forming cavities in...
US20120319246 IP PROTECTION  
Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.
US20120299158 CMP POLISHING LIQUID, METHOD FOR POLISHING SUBSTRATE, AND ELECTRONIC COMPONENT  
The CMP polishing liquid of the invention is used by mixing a first solution and a second solution, the first solution comprises cerium-based abrasive grains, a dispersant and water, the second...
US20140084422 Reclaimed Wafer And A Method For Reclaiming A Wafer  
Embodiments of the present invention relate to a reclaimed wafer, a method for reclaiming a wafer, a method for reclaiming a batch of wafers, and a method for forming electronic structures. After...
US20130049158 FORMATION OF METAL NANOSPHERES AND MICROSPHERES  
Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface...
US20110248386 METHOD OF FORMATION OF COHERENT WAVY NANOSTRUCTURES (VARIANTS)  
The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying...
US20130299945 FABRICATE SELF-FORMED NANOMETER PORE ARRAY AT WAFER SCALE FOR DNA SEQUENCING  
A technique is provided for a structure. A substrate has a nanopillar vertically positioned on the substrate. A bottom layer is formed beneath the substrate. A top layer is formed on top of the...
US20120038030 METHOD FOR FILLING CAVITIES IN WAFERS, CORRESPONDINGLY FILLED BLIND HOLE AND WAFER HAVING CORRESPONDINGLY FILLED INSULATION TRENCHES  
A method is described for filling cavities in wafers, the cavities being open to a predetermined surface of the wafer, including the following steps: applying a lacquer-like filling material to...
US20150228498 METHOD FOR MANUFACTURING ADHESIVE FILM FOR IMPRINTS AND METHOD FOR FORMING PATTERNS  
To obtain a good pattern having a good profile of etched pattern. A method for manufacturing an adhesive film for imprints, the method comprising applying an adhesive composition for imprints in a...
US20110041898 Back Metal Layers in Inverted Metamorphic Multijunction Solar Cells  
A multijunction solar cell comprising an upper first solar subcell having a first band gap; a middle second solar subcell adjacent to the first solar subcell and having a second band gap smaller...
US20120326278 METHOD TO SOLVE POTENTIAL YIELD LOSS DUE TO METAL MIGRATION TO WIRE ROUTING NETS FROM FIDUCIARY MARKS ON PRODUCT DURING CHEMICAL-MECHANICAL-POLISHING (CMP) PLANARIZATION PROCESSING STEPS  
A mask for a semiconductor process step includes an indicia section. The indicia section on the mask is used to produce a field of separated polygon elements with a defined negative space in the...
US20090224370 NON-PLANAR CVD DIAMOND-COATED CMP PAD CONDITIONER AND METHOD FOR MANUFACTURING  
The present invention relates to a composite material having non-planar geometries and edge-shaving surfaces comprising a CVD diamond coating applied to a composite substrate made from a ceramic...
US20110163420 ASPECT RATIO ADJUSTMENT OF MASK PATTERN USING TRIMMING TO ALTER GEOMETRY OF PHOTORESIST FEATURES  
A method for adjusting the geometry of photomask patterns is provided. Such adjusted pattern can be employed to achieve pattern doubling in subsequent layers. A patterned photoresist mask is...
US20130037915 Method and Apparatus for Providing a Layout Defining a Structure to be Patterned onto a Substrate  
A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid...
US20140015108 METHOD OF MANUFACTURING SINGLE CRYSTAL INGOT, AND SINGLE CRYSTAL INGOT AND WAFER MANUFACTURED THEREBY  
A method of manufacturing a single crystal ingot, and a single crystal ingot and a wafer manufactured thereby are provided. The method of manufacturing a single crystal ingot according to an...
US20090174036 PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES  
A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line...
US20110127643 METHOD AND APPARATUS FOR CONFORMABLE POLISHING  
A multi-station polish system and process for polishing thin, flat (planar) and rigid workpieces. Workpieces are conveyed through multiple polishing stations that include a bulk material removal...
US20120161292 PROCESS FOR ASSEMBLING TWO WAFERS AND CORRESPONDING DEVICE  
A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to...
US20130270681 SILICON WAFER AND FABRICATION METHOD THEREOF  
A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first...
US20110227202 SILICON WAFER AND FABRICATION METHOD THEREOF  
A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first...
US20090309192 INTEGRATED CIRCUIT SYSTEM WITH SUB-GEOMETRY REMOVAL AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell,...
US20080296734 MICROCHIP AND METHOD OF MANUFACTURING MICROCHIP  
A microchip formed by joining a first substrate having at least one recess on its surface and a second substrate, wherein small projections of 0.5 to 30 μm in height are formed on at least a part...
US20100006865 SEMICONDUCTOR MODULE FOR POWER GENERATION OR LIGHT EMISSION  
In order to collect a plurality of semiconductor elements easily from a semiconductor module where a plurality of rod-like semiconductor elements for power generation or light emission are built...
US20130153026 SUBSTRATE FOR SOLAR CELL, AND SOLAR CELL  
Provided is a substrate for a solar cell, wherein a flat chamfered portion is formed on one corner of a silicon substrate having a square shape in a planar view, or a notch is formed on the corner...
US20130334667 Alkaline Etching Liquid for Texturing a Silicon Wafer Surface  
An etching liquid for texturing a silicon wafer surface is provided. The etching liquid may include an aqueous solution of at least one alkaline etching agent and at least one polysaccharide or...
US20120112321 ALKALINE ETCHING LIQUID FOR TEXTURING A SILICON WAFER SURFACE  
An etching liquid for texturing a silicon wafer surface is provided. The etching liquid may include an aqueous solution of at least one alkaline etching agent and at least one polysaccharide or...
US20140015107 METHOD TO IMPROVE WITHIN WAFER UNIFORMITY OF CMP PROCESS  
Closed loop control may be used to improve uniformity of within wafer uniformity using chemical mechanical planarization. For example, closed loop control may be used to determine a control...
US20110193197 STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS  
A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding...
US20140117504 EPHEMERAL BONDING  
Compositions containing an adhesive material and a release additive are suitable for temporarily bonding two surfaces, such as a wafer active side and a substrate. These compositions are useful in...
US20070102791 STRUCTURE OF MULTI-LAYER CRACK STOP RING AND WAFER HAVING THE SAME  
A multi-layer crack stop ring structure disposed between a die seal ring and a scribe line or disposed between a dual die seal ring is provided. The multi-layer crack stop ring structure does not...
US20130069057 WAFER WITH HIGH RUPTURE RESISTANCE  
A wafer with high rupture resistance includes a plurality of surfaces, wherein the surfaces include a largest surface having a largest area than others and a side surface connected to the fringe...