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US20070267715 Shallow trench isolation (STI) with trench liner of increased thickness  
Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a...
US20130009277 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR  
A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a...
US20110006390 STI STRUCTURE AND METHOD OF FORMING BOTTOM VOID IN SAME  
A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the...
US20080040696 Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2  
Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes shallow trench isolation filled with liquid phase...
US20090127626 STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION  
A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the...
US20110108991 CIRCUIT LAYOUT STRUCTURE  
A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal...
US20130200488 STRUCTURES AND TECHNIQUES FOR USING MESH-STRUCTURE DIODES FOR ELECTRO-STATIC DISCHARGE (ESD) PROTECTION  
An Electro-Static Discharge (ESD) protection using at least one I/O pad with at least one mesh structure of diodes provided on a semiconductor body is disclosed. The mesh structure has a plurality...
US20120012974 LATERAL TRANSIENT VOLTAGE SUPPRESSOR FOR LOW-VOLTAGE APPLICATIONS  
A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally...
US20050275059 Isolation trench arrangement  
Isolation trench arrangement, which isolates adjacent semiconductor structures (1), (2), an isolation trench (3) being formed in such a way that it penetrates from a substrate surface into the...
US20150137253 Stress-inducing Structures, Methods, and Materials  
Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a...
US20070246795 Dual depth shallow trench isolation and methods to form same  
Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes...
US20070102783 Insultating structures  
An electrical insulator comprises an elongate shank and one or more sheds disposed along the length of the shank. The surface of the insulator comprises longitudinally extending flutes, the depth...
US20060186509 Shallow trench isolation structure with active edge isolation  
A method of fabricating a shallow trench isolation (STI) structure with active edge isolation and increased radiation hardening is presented. The invention comprises forming a pad oxide layer on a...
US20120012973 LATERAL TRANSIENT VOLTAGE SUPPRESSOR WITH ULTRA LOW CAPACITANCE  
A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type...
US20070132058 Adjuvant for controlling polishing selectivity and chemical mechanical polishing slurry comprising the same  
Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms an adsorption layer on the cationically charged...
US20100006974 STORAGE NITRIDE ENCAPSULATION FOR NON-PLANAR SONOS NAND FLASH CHARGE RETENTION  
The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate,...
US20150170957 ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME  
A method of forming a semiconductor structure includes implanting neutral dopants in a first region of a substrate to form a first etching stop feature, the first etching stop feature having a...
US20050073021 Selective etch shallow trench isolation barrier integrated circuit chip and fabrication method  
The selective etch shallow trench isolation barrier integrated circuit fabrication system and method of the present invention minimizes the layers required to implement a shallow trench isolation...
US20090045482 Shallow Trench Isolation with Improved Structure and Method of Forming  
A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a...
US20140167213 Moat Construction to Reduce Noise Coupling to a Quiet Supply  
A semiconductor chip having a P− substrate and an N+ epitaxial layer grown on the P− substrate is shown. A P− circuit layer is grown on top of the N+ epitaxial layer. A first moat having an...
US20090072347 Semiconductor Constructions, and Electronic Systems  
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor...
US20070045769 Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions  
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over...
US20050205963 Integrated anneal cap/ ion implant mask/ trench isolation structure for III-V devices  
A structure with significant topography enhancements over the traditional composite dielectric structure is provided. Topography reduction at this level of the device structure significantly...
US20080217714 SEMICONDUCTOR DEVICE HAVING TILES FOR DUAL-TRENCH INTEGRATION AND METHOD THEREFOR  
A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second...
US20100065941 INTERMEDIATE SEMICONDUCTOR STRUCTURES  
An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening...
US20120074496 Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same  
Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing...
US20100219501 TRENCH ISOLATION IMPLANTATION  
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material....
US20100038744 Shallow Trench Isolation  
Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a...
US20080157264 Shallow trench isolation devices and methods  
One embodiment of the present invention relates to a method of forming an isolation structure. During this method, an isolation trench is formed within a semiconductor body. After this trench is...
US20080040697 Design Structure Incorporating Semiconductor Device Structures with Voids  
Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a gate electrode of a device, such as a field effect...
US20090032900 METHOD OF PROTECTING SHALLOW TRENCH ISOLATION STRUCTURE AND COMPOSITE STRUCTURE RESULTING FROM THE SAME  
A method of protecting a shallow trench isolation structure is described, which is applied to a semiconductor device process that includes a first process causing a recess in the STI structure and...
US20110241158 ISOLATION TRENCHES  
A method is for the formation of at least one filled isolation trench having a protective cap in a semiconductor layer, and a semiconductor device with at least one filled isolation trench having...
US20110037142 SOI WAFER AND METHOD FOR FORMING THE SAME  
An SOI wafer and a method for forming the same, where the method for forming an SOI wafer includes: preparing a monocrystalline silicon wafer on which a mask layer is formed; etching the mask...
US20050156273 Memory devices  
A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation...
US20110284985 SHALLOW TRENCH ISOLATION EXTENSION  
A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An...
US20060076640 Semiconductor device  
A semiconductor device, comprising a trench extending into the device from a surface. The trench has sidewalls extending along the length of the trench, a depth and a width defined at said surface...
US20120241903 LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR  
A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode...
US20150069571 HEAT DISSIPATION THROUGH DEVICE ISOLATION  
According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film...
US20130154051 METHOD FOR FORMING A DEEP TRENCH IN A MICROELECTRONIC COMPONENT SUBSTRATE  
A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The...
US20110024871 SEMICONDUCTOR STRUCTURE  
A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched...
US20070235835 Shallow trench isolation structure for semiconductor device  
A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler...
US20130043555 ELECTROSTATIC DISCHARGE (ESD) PROTECTION ELEMENT AND ESD CIRCUIT THEREOF  
An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped...
US20090283852 Stress-Inducing Structures, Methods, and Materials  
Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a...
US20110024836 Field Effect Transistor With Trench-Isolated Drain  
A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a...
US20110284986 BYPASS DIODE FOR A SOLAR CELL  
Bypass diodes for solar cells are described. In one embodiment, a bypass diode for a solar cell includes a substrate of the solar cell. A first conductive region is disposed above the substrate,...
US20070170542 Method of filling a high aspect ratio trench isolation region and resulting structure  
A method of filling a high aspect ratio trench isolation region, which allows for better gap-fill characteristics and avoids voids and seams in the isolation region. The method includes the steps...
US20100252907 Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same  
A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a...
US20050167777 Microelectronic device with active layer bumper  
A method comprises providing a substrate having an active layer, forming an isolation trench in the active layer, and forming at least one bumper substantially filling at least one divot formed at...
US20090079026 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES  
A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a...
US20050085089 Etching apparatus, semiconductor devices and methods of fabricating semiconductor devices  
Etching apparatus, semiconductor devices and methods for fabricating semiconductor devices are disclosed. An example semiconductor device comprises: a semiconductor substrate; and a trench formed...

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