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US20130285190 Layout of a MOS Array Edge with Density Gradient Smoothing  
A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered...
US20110133304 Structure and Method for Placement, Sizing and Shaping of Dummy Structures  
A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy...
US20090108257 CRITICAL DIMENSION FOR TRENCH AND VIAS  
Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed...
US20060270183 Isolation structure and method of forming the same  
An isolation structure may include a trench formed on a surface of a substrate. A first isolation pattern may be provided on an inner face of the trench to define an auxiliary trench. A second...
US20080224251 Optimal Rasterization for Maskless Lithography  
A lithographic system is provided in which an extent of overlap between pattern sections is adjusted in order to match a size of a pattern section to a size of a repeating portion of the pattern...
US20050205961 Model-based insertion of irregular dummy features  
A semiconductor device includes an electric circuit, a first conductive feature coupled to the electric circuit, a dielectric material isolating the first conductive feature, and at least two...
US20110221029 BALANCED ADAPTIVE BODY BIAS CONTROL  
Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a...
US20130214380 AREA AND POWER SAVING STANDARD CELL METHODOLOGY  
A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at...
US20140339672 WAFER DIE SEPARATION  
A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet to a ring frame; relatively raising...
US20130193554 Cell Array with Density Features  
A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using...
US20130087880 MEMS DEVICE AND METHOD OF MANUFACTURE  
A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels,...
US20090278222 INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE  
Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes...
US20120038019 MEMS Device and Fabrication Method  
A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top...
US20110127633 Slotted Configuration for Optimized Placement of Micro-Components using Adhesive Bonding  
An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the...
US20130241025 ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS  
An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on...
US20120153425 PROCESS FOR FABRICATING INTEGRATED-CIRCUIT CHIPS  
Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at...
US20070252230 CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD  
A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress...
US20140035091 Electrostatic Discharge Protection Circuit Including a Distributed Diode String  
An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the first terminal and a power supply...
US20110204449 Dummy Pattern Design for Reducing Device Performance Drift  
A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region...
US20140117488 PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES  
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated,...
US20140167206 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE  
A semiconductor device includes a substrate and a first and second plurality of stack structures arranged over the substrate. The first and second plurality of stack structures are separated by a...
US20140339673 WAFER PROCESSING  
A method of separating dies of a singulated wafer is disclosed. The method may include supporting the singulated wafer on a supporting portion of a sheet of dicing tape that has a first ring...
US20120292735 CORNER TRANSISTOR SUPPRESSION  
The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments...
US20140175594 ACTIVE PAD PATTERNS FOR GATE ALIGNMENT MARKS  
Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the...
US20080227302 FIBROUS LAMINATE INTERFACE FOR SECURITY COATINGS  
an integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and...
US20150262936 MULTI SUPPLY CELL ARRAYS FOR LOW POWER DESIGNS  
A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells...
US20140167128 Memory Gate Landing Pad Made From Dummy Features  
Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at...
US20070052059 Structure for decreasing minimum feature size in an integrated circuit  
A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the...
US20090321870 SHUTTLE WAFER AND METHOD OF FABRICATING THE SAME  
A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the...
US20140001595 Layout Architecture for Performance Improvement  
An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a...
US20090319973 SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION  
A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is...
US20090032899 Integrated circuit design based on scan design technology  
An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to...
US20090085148 MULTI-DIRECTIONAL TRENCHING OF A PLURALITY OF DIES IN MANUFACTURING SUPERJUNCTION DEVICES  
A method of manufacturing a superjunction device includes providing a semiconductor wafer having a plurality of dies. A first plurality of trenches having a first orientation are formed in a first...
US20090267175 DOUBLE PATTERNING TECHNIQUES AND STRUCTURES  
Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated...
US20120097208 METHOD FOR THE PRODUCTION AND SERIES CONNECTION OF STRIP-SHAPED ELEMENTS ON A SUBSTRATE  
Provided is a method for generating, and for connecting in series, stripe-shaped elements, wherein less space is required for the series connection as compared to the prior art.
US20100289111 System and Method for Designing Cell Rows  
A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard...
US20090085147 MULTI-DIRECTIONAL TRENCHING OF A DIE IN MANUFACTURING SUPERJUNCTION DEVICES  
A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least...
US20080217726 INTEGRATED CIRCUIT SYSTEM EMPLOYING DIPOLE MULTIPLE EXPOSURE  
An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist...
US20140225218 ION REDUCED, ION CUT-FORMED THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DICS), AND RELATED METHODS AND SYSTEMS  
Ion-reduced, ion cut-formed three-dimensional (3D) integrated circuits (IC) (3DICs) are disclosed. Related methods and systems are also disclosed. During an ion-cut process for forming a...
US20130256833 TRIPLE WELL ISOLATED DIODE AND METHOD OF MAKING  
A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple...
US20100078701 THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING REPEATING LAYER PATTERNS OF DIFFERENT THICKNESSES  
A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a...
US20110042784 Mechanical Barrier Element for Improved Thermal Reliability of Electronic Components  
Embodiments of the invention are generally related to packaging of integrated circuit devices, and more specifically to the placement of thermal paste for cooling an integrated circuit device...
US20120306045 Active Tiling Placement for Improved Latch-Up Immunity  
A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well...
US20100320558 CIRCUIT LAYOUT STRUCTURE AND METHOD TO SCALE DOWN IC LAYOUT  
A circuit layout structure includes a substrate including a first region and a second region, and a set of conductive lines including a first conductive line and a second conductive line which...
US20150115393 METHODS OF STRESS BALANCING IN GALLIUM ARSENIDE WAFER PROCESSING  
Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a...
US20090140371 Semiconductor integrated device and manufacturing method for the same  
A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first...
US20070175862 Anisotropic etching agent composition used for manufacturing of micro-structures of silicon and etching method  
An anisotropic etching agent composition for manufacturing of micro-structures of silicon comprising an alkali compound and hydroxylamines; an anisotropic etching method with the use of the...
US20130313677 STRUCTURE FOR PICKING UP A COLLECTOR AND MANUFACTURING METHOD THEREOF  
A structure for picking up a collector region is disclosed. The structure includes a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair...
US20130043553 DUMMY FILL TO REDUCE SHALLOW TRENCH ISOLATION (STI) STRESS VARIATION ON TRANSISTOR PERFORMANCE  
An integrated circuit includes an active layer including an active pattern diffusion region. The integrated circuit further includes at least one guard band conforming to a shape of the active...
US20060091355 Solution and method for removing ashing residue in Cu/low-k multilevel interconnection structure  
The present invention relates to a removing solution for removing ashing residue formed by dry etching and/or ashing on a Cu/low-k multilevel interconnection structure, wherein the removing...

Matches 1 - 50 out of 334 1 2 3 4 5 6 7 >