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US20150170983 PROBE PAD DESIGN TO REDUCE SAW DEFECTS  
An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad...
US20050098778 Burn-in test adapter and burn-in test apparatus  
An assembly substrate, on which semiconductor chips, each having a terminal receiving a burn-in test waveform, are arranged, is detachably attached to a burn-in test adapter. The burn-in test...
US20090108257 CRITICAL DIMENSION FOR TRENCH AND VIAS  
Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed...
US20080197351 TESTKEY DESIGN PATTERN FOR GATE OXIDE  
A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one...
US20140014959 PASSIVATION LAYER FOR PACKAGED CHIP  
A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first...
US20090152544 DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE  
A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical...
US20140002121 SYSTEM AND METHOD FOR ELECTRONIC TESTING OF PARTIALLY PROCESSED DEVICES  
Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for...
US20130141114 NON-LINEAR KERF MONITOR AND DESIGN STRUCTURE THEREOF  
A non-linear kerf monitor, methods of manufacture and design structures are provided. The structure includes a coplanar waveguide provided in a kerf of a wafer between a first chip and a second...
US20130140563 Plating Process and Structure  
A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another...
US20130082257 VIA CHAINS FOR DEFECT LOCALIZATION  
Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via...
US20110156032 METHOD OF REPAIRING PROBE PADS  
A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad...
US20110292733 ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF  
A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed...
US20120119778 POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES  
A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the...
US20130168675 Detection and Mitigation of Particle Contaminants in MEMS Devices  
Detecting and/or mitigating the presence of particle contaminants in a MEMS device involves including MEMS structures that in normal operation are robust against the presence of particles but...
US20130048980 INTEGRATED CIRCUITS WITH LEAKAGE CURRENT TEST STRUCTURE  
An integrated circuit includes a seal ring structure disposed around a circuit that is disposed over a substrate. A first pad is electrically coupled with the seal ring structure. A leakage...
US20130026466 TESTING ARCHITECTURE OF CIRCUITS INTEGRATED ON A WAFER  
An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing...
US20110266539 High Performance Compliant Wafer Test Probe  
An electrical connection includes a first electrical contact made of electrically conductive material. The first electrical contact is formed with a depression therein. Also included are a...
US20140203828 LAYOUT STRUCTURE OF ELECTRONIC ELEMENT AND TESTING METHOD OF THE SAME THEREOF  
A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and...
US20090045400 Method for monitoring fuse integrity in a semiconductor die and related structure  
According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure,...
US20150262899 METHOD AND STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY  
A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the...
US20120293191 HVMOS Reliability Evaluation using Bulk Resistances as Indices  
A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device...
US20150112623 STRUCTURE FOR MEASURING DOPING REGION RESISTANCE AND METHOD OF MEASURING CRITICAL DIMENSION OF SPACER  
A method of the measuring a critical dimension of a spacer is provided. The measurement is performed by using several test structures of measuring doping region resistance. Each of the test...
US20150041809 VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION  
A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second...
US20140145191 VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION  
A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second...
US20110168995 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits  
Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by...
US20100320461 INTEGRATION OF SENSE FET INTO DISCRETE POWER MOSFET  
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical...
US20070148796 ZQ calibration circuit and semiconductor device  
AZQ calibration command internally generated from an external command different from a ZQ calbration command so as to automatically perform an additional ZQ calibration operation. A command...
US20070248898 TARGETS FOR ALIGNMENT OF SEMICONDUCTOR MASKS  
Alignment of mask layers in semiconductor manufacturing is carried out by using alignment lines having at least one row of diffractively reflecting or scattering features on the lines. The...
US20070284577 Semiconductor device including fuses and method of cutting the fuses  
A semiconductor device may include multiple fuses spaced at a same pitch from each other and a check pattern spaced a predetermined distance from one side of the fuses, where the check pattern has...
US20120181535 PHOTOELECTRIC CONVERSION MODULE AND METHOD OF MANUFACTURING THE SAME  
A photoelectric conversion module includes a circuit board including a plurality of first board-side electrodes and a plurality of second board-side electrodes that are alternately arranged on a...
US20140225110 Default Trim Code Technique  
In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the...
US20080157076 Semiconductor device with test pads and pad connection unit  
A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples...
US20150206809 WAFER THINNING ENDPOINT DETECTION FOR TSV TECHNOLOGY  
Embodiments of the present invention provide an apparatus and method for wafer thinning endpoint detection. Embodiments of the present invention utilize through silicon via (TSV) structures formed...
US20140346513 Mixed-Sized Pillars That Are Probeable and Routable  
An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and...
US20120080673 Crack Stop Barrier and Method of Manufacturing Thereof  
A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier.
US20090095955 SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF  
A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the...
US20130001550 HERMETICALLY SEALED MEMS DEVICE WITH A PORTION EXPOSED TO THE ENVIRONMENT WITH VERTICALLY INTEGRATED ELECTRONICS  
A system and method for providing a MEMS device with integrated electronics are disclosed. The MEMS device comprises an integrated circuit substrate and a MEMS subassembly coupled to the...
US20120248438 FAULT-TOLERANT UNIT AND METHOD FOR THROUGH-SILICON VIA  
A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a...
US20130299828 VIA CHAINS FOR DEFECT LOCALIZATION  
Via chain and serpentine/comb test structures are in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test...
US20130082258 METHOD FOR STRIP TESTING OF MEMS DEVICES, TESTING STRIP OF MEMS DEVICES AND MEMS DEVICE THEREOF  
A method for testing a strip of MEMS devices, the MEMS devices including at least a respective die of semiconductor material coupled to an internal surface of a common substrate and covered by a...
US20090206865 ELECTRICAL TEST STRUCTURE AND METHOD FOR CHARACTERIZATION OF DEEP TRENCH SIDEWALL RELIABILITY  
A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation...
US20150115982 Structures and Methds for Monitoring Dielectric Reliability With Through-Silicon Vias  
Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to...
US20100308329 LITHOGRAPHY ROBUSTNESS MONITOR  
The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated...
US20060278871 Detecting and improving bond pad connectivity with pad check  
A method for analyzing an integrated circuit (or constituent parts thereof), a computer program implementing the method, and a computer configured to execute the program is disclosed. Analyzing...
US20080278190 Testing fuse configurations in semiconductor devices  
Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external...
US20150076498 TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS  
A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro...
US20100045325 Test Pad Design for Reducing the Effect of Contact Resistances  
An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and...
US20130119382 Plating Process and Structure  
A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the...
US20090002012 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits  
Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by...
US20150115994 OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY  
A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The...