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US20110186937 ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION  
A self-aligned well implantation process may be performed so as to adjust threshold voltage and/or body resistance of transistors. To this end, after removing a placeholder material of gate...
US20120139051 SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS  
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate...
US20110127617 PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY AN EARLY EXTENSION IMPLANTATION  
In sophisticated transistor elements, integrity of sensitive gate materials may be enhanced while, at the same time, the lateral offset of extension regions may be reduced. To this end, at least a...
US20110079861 Advanced Transistors with Threshold Voltage Set Dopant Structures  
An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned...
US20150194515 Programmable antenna controlled impedance mosfet  
Hop frequency radio technologies use dynamic modulation frequency control through a single antenna with non-ideal performance as antenna length is inversely proportional to modulation frequency....
US20110089495 APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS  
Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high...
US20130146992 DEEP TRENCH EMBEDDED GATE TRANSISTOR  
A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the...
US20120326752 DESIGN METHOD AND STRUCTURE FOR A TRANSISTOR HAVING A RELATIVELY LARGE THRESHOLD VOLTAGE VARIATION RANGE AND FOR A RANDOM NUMBER GENERATOR INCORPORATING MULTIPLE ESSENTIALLY IDENTICAL TRANSISTORS HAVING SUCH A LARGE THRESHOLD VOLTAGE VARIATION RANGE  
Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF...
US20140021545 POCKET COUNTERDOPING FOR GATE-EDGE DIODE LEAKAGE REDUCTION  
A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate...
US20120126341 USING LOW PRESSURE EPI TO ENABLE LOW RDSON FET  
A method for forming an epitaxial layer on a substrate may have the steps of: forming a heavily doped silicon substrate; depositing an epitaxial layer at sub atmospheric pressure on the heavily...
US20150041904 BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING  
A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a...
US20130113050 BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING  
A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a...
US20100025777 METHOD FOR SUPPRESSING LATTICE DEFECTS IN A SEMICONDUCTOR SUBSTRATE  
A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these...
US20150076622 REDUCING GATE EXPANSION AFTER SOURCE AND DRAIN IMPLANT IN GATE LAST PROCESS  
A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide...
US20130181298 ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION  
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and...
US20110121404 ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION  
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and...
US20090273040 HIGH PERFORMANCE SCHOTTKY-BARRIER-SOURCE ASYMMETRIC MOSFETS  
The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain...
US20130134523 CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS  
CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers...
US20140264431 ENHANCEMENT-MODE III-NITRIDE DEVICES  
A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator...
US20150015337 MODULAR APPROACH FOR REDUCING FLICKER NOISE OF MOSFETS  
In one example implementation, the present disclosure provides a modular approach to reducing flicker noise in metal-oxide semiconductor field-effect transistors (MOSFETs) in a device. First, a...
US20140239415 STRESS MEMORIZATION IN RMG FINFETS  
Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate...
US20090267161 INCREASING BODY DOPANT UNIFORMITY IN MULTI-GATE TRANSISTOR DEVICES  
Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a...
US20110012208 FIELD-EFFECT TRANSISTOR WITH LOCAL SOURCE/DRAIN INSULATION AND ASSOCIATED METHOD OF PRODUCTION  
A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a...
US20080023752 BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT  
An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate;...
US20120168874 STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC  
Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material...
US20100200934 FIELD EFFECT DEVICE INCLUDNG RECESSED AND ALIGNED GERMANIUM CONTAINING CHANNEL  
A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium...
US20100065923 III-NITRIDE DEVICE WITH BACK-GATE AND FIELD PLATE AND PROCESS FOR ITS MANUFACTURE  
A III-Nitride device has a back-gate disposed in a trench and under and in close proximity to the 2 DEG layer and in lateral alignment with the main gate of the device. A laterally disposed trench...
US20110079860 TUNNEL FIELD EFFECT TRANSISTOR WITH IMPROVED SUBTHRESHOLD SWING  
The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being...
US20110031554 STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC  
A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate...
US20090127636 Diffusion Variability Control and Transistor Device Sizing Using Threshold Voltage Implant  
A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is...
US20070228495 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME  
An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion...
US20110095379 SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT  
A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the...
US20130009255 FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD  
Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel...
US20110127618 PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT  
In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a...
US20120126340 CMOS Devices With Reduced Short Channel Effects  
An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration...
US20120223390 TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FORMING THE SAME  
The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a...
US20120273900 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third...
US20090085125 MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors  
Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS...
US20130249019 FinFET with Metal Gate Stressor  
A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on...
US20150108586 TRANSISTOR DEVICE WITH IMPROVED SOURCE/DRAIN JUNCTION ARCHITECTURE AND METHODS OF MAKING SUCH A DEVICE  
One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having...
US20150001640 TRANSISTOR DEVICE WITH IMPROVED SOURCE/DRAIN JUNCTION ARCHITECTURE AND METHODS OF MAKING SUCH A DEVICE  
One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having...
US20140232433 CIRCUIT ELEMENT INCLUDING A LAYER OF A STRESS-CREATING MATERIAL PROVIDING A VARIABLE STRESS AND METHOD FOR THE FORMATION THEREOF  
A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable...
US20070145495 Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance  
A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing...
US20100181629 METHOD OF FORMING AN INTEGRATED CIRCUIT  
A method includes forming a source, a drain, and a disposable gate (38) of the first transistor; forming a source, a drain, and a disposable gate of the second transistor; removing the disposable...
US20150137268 NON-PLANAR SIGE CHANNEL PFET  
Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a channel layer formed of a Germanium compound having a...
US20110147845 Remote Doped High Performance Transistor Having Improved Subthreshold Characteristics  
Devices comprising, and a method for fabricating, a remote doped high performance transistor having improved subthreshold characteristics are disclosed. In one embodiment a field-effect transistor...
US20110193177 ELECTRONIC DEVICE INCLUDING A DOPED REGION DISPOSED UNDER AND HAVING A HIGHER DOPANT CONCENTRATION THAN A CHANNEL REGION AND A PROCESS OF FORMING THE SAME  
An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not...
US20140252498 METHOD FOR FABRICATING A FIELD EFFECT TRANSISTOR, AND FIELD EFFECT TRANSISTOR  
In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first...
US20130105915 METAL OXIDE SEMICONDUCTOR DEVICE HAVING A PREDETERMINED THRESHOLD VOLTAGE AND A METHOD OF MAKING  
A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type...
US20120056258 ELECTRICAL SWITCH USING GATED RESISTOR STRUCTURES AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING THE SAME  
An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the...

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