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US20150187903 FRINGE CAPACITANCE REDUCTION FOR REPLACEMENT GATE CMOS  
A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench
US20140264629 LOCAL INTERCONNECT STRUCTURES FOR HIGH DENSITY  
A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.
US20120112819 ELECTROMIGRATION-COMPLAINT HIGH PERFORMANCE FET LAYOUT  
An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one...
US20150145070 MERGING LITHOGRAPHY PROCESSES FOR GATE PATTERNING  
Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon...
US20130277761 MOTOR CONTROL MULTILAYER CIRCUIT BOARD  
A motor control multilayer printed wiring board includes: a multilayer printed wiring board having a plurality of laminated conductor layers; an upper-row FET connected to the conductor layers and...
US20120119305 LAYOUT OF POWER MOSFET  
A layout of a power MOSFET includes a first zigzag gate structure located on a substrate of the power MOSFET and having a first side and a second side, a first contact located on the substrate and...
US20110186930 RING POWER GATING WITH DISTRIBUTED CURRENTS USING NON-LINEAR C4 CONTACT PLACEMENTS  
A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on...
US20120126338 CROSS-HAIR CELL DEVICES AND METHODS FOR MANUFACTURING THE SAME  
Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In one embodiment, a process may include...
US20150255458 REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION  
A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric...
US20130069169 ECO LOGIC CELL AND DESIGN CHANGE METHOD USING ECO LOGIC CELL  
The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks...
US20150069530 INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME  
An integrated circuit comprises a gate electrode of at least one active transistor. The integrated circuit also comprises a first dummy gate electrode on a first side of the gate electrode. The...
US20150137267 REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING  
Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further...
US20140175565 Integrated Circuit Cell Library for Multiple Patterning  
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array...
US20120273899 SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN  
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET...
US20140131816 CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES  
An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a...
US20110074511 LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG  
A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source...
US20100314693 INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET  
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common...
US20110298059 INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME  
An integrated circuit includes at least one first gate electrode of at least one active transistor. At least one first dummy gate electrode is disposed adjacent to a first side edge of the at...
US20140015005 SINGLE CHIP IGNITER AND INTERNAL COMBUSTION ENGINE IGNITION DEVICE  
Aspects of the invention are directed to a single chip igniter such that it is possible to realize a reduction in operating voltage, an increase in noise tolerance, a reduction in size, and a...
US20130093028 INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME  
An integrated circuit includes at least one first gate electrode of at least one active transistor. The integrated circuit further includes at least one first dummy gate electrode and at least one...
US20100327374 LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS  
An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D...
US20130099324 GAN-ON-SI SWITCH DEVICES  
A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an...
US20050275043 Novel semiconductor device design  
An integrated circuit having small layout area and a method of forming the same are provided. A slant contact is formed by shifting a portion of a contact a distance less than a whole dimension of...
US20150097249 CROSS COUPLING GATE USING MULITPLE PATTERNING  
Methodologies for forming a cross coupling gate and a resulting device are disclosed. Embodiments include: providing a plurality of gates extending vertically on a plurality of equally spaced...
US20080048272 SILICIDATION MONITORING PATTERN FOR USE IN SEMICONDUCTOR MANUFACTURING PROCESS  
A silicidation monitoring pattern may electrically measure resistance of a polygate line after silicidation to measure open and/or short-circuiting of the polygate line. A silicidation monitoring...
US20150171080 Radio Frequency and Microwave Devices and Methods of Use  
Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor...
US20150054091 Radio Frequency and Microwave Devices and Methods of Use  
Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor...
US20120292716 DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF  
A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and...
US20130207200 INTEGRATED CIRCUIT HAVING THINNER GATE DIELECTRIC AND METHOD OF MAKING  
An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate...
US20090057780 FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS  
A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due...
US20120242378 FREQUENCY DIVIDER CIRCUIT  
A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The...
US20090250770 INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET  
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common...
US20150035077 MOS TRANSISTORS INCLUDING A RECESSED METAL PATTERN IN A TRENCH  
Methods of manufacturing a MOS transistor are provided. The methods may include forming first and second trenches. The methods may further include forming first metal patterns within portions of...
US20120032276 N-WELL/P-WELL STRAP STRUCTURES  
Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
US20140103449 OXYGEN FREE RTA ON GATE FIRST HKMG STACKS  
A method of fabricating a semiconductor device with improved Vt and the resulting device are disclosed. Embodiments include forming an HKMG stack on a substrate; implanting dopants in active...
US20140239412 Channel Doping Extension beyond Cell Boundaries  
An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The...
US20120139058 POWER MOS DEVICE  
A power MOS device having a gate with crosshatched lattice pattern on a substrate and at lease a source or a drain isolated by the gate, characterized in that the source has only one diffusion...
US20130069170 ILLUMINATION AND DESIGN RULE METHOD FOR DOUBLE PATTERNED SLOTTED CONTACTS  
An integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates...
US20120119306 METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF  
A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate...
US20150194497 METHOD OF FORMING CHANNEL OF GATE STRUCTURE  
A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the...
US20130062707 DUMMY CELL PATTERN FOR IMPROVING DEVICE THERMAL UNIFORMITY  
A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A;...
US20140110794 FACILITATING GATE HEIGHT UNIFORMITY AND INTER-LAYER DIELECTRIC PROTECTION  
Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate...
US20140175514 RING-SHAPED TRANSISTORS PROVIDING REDUCED SELF-HEATING  
A ring-shaped transistor includes a set of gates. Each gate of the set is disposed between a corresponding source and a corresponding drain. The set of gates are arranged such that all of the set...
US20120061771 MOSFET LAYOUT AND STRUCTURE  
A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain...
US20150187702 MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES  
An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography...
US20140027862 RF CMOS TRANSISTOR DESIGN  
An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source...
US20110241126 RF CMOS TRANSISTOR DESIGN  
An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source...
US20150054093 FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE  
FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt...
US20130307087 METHOD FOR FORMING A SELF-ALIGNED CONTACT OPENING BY A LATERAL ETCH  
A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an...
US20150155280 IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE  
A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and...