Matches 1 - 42 out of 42


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US20090294872 Ge/Xe IMPLANTS TO REDUCE JUNCTION CAPACITANCE AND LEAKAGE  
A method of reducing junction capacitance and leakage and a structure having reduced junction capacitance and leakage wherein germanium or xenon is implanted in the source and drain regions to at...
US20090315120 RAISED FACET- AND NON-FACET 3D SOURCE/DRAIN CONTACTS IN MOSFETS  
An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the...
US20090278207 Electromigration-Complaint High Performance FET Layout  
An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one...
US20100025775 Replacement spacers for mosfet fringe capacatance reduction and processes of making same  
A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing...
US20080224233 Igfet Device Having a Rf Capability  
An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first...
US20090020830 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD  
Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs)...
US20080111197 SEMICONDUCTOR DEVICE INCLUDING A MISFET HAVING DIVIDED SOURCE/DRAIN REGIONS  
A MISFET includes source/drain regions each including a plurality of divided substrate regions divided by intervening insulation films, and a selectively-grown silicon layer formed on the divided...
US20140332898 FANOUT LINE STRUCTURE OFARRAY SUBSTRATE AND DISPLAY PANEL  
A fanout line structure of an array substrate includes a plurality of fanout lines arranged on a fanout area of the array substrate, where resistance value of the fanout line is dependent on...
US20110084325 DRAM STRUCTURE WITH A LOW PARASITIC CAPACITANCE AND METHOD OF MAKING THE SAME  
An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory...
US20080197423 Device and method for reducing a voltage dependent capacitive coupling  
A device comprises a first means for separating a conductive layer from a semiconductor substrate and a second means for reducing a voltage dependent capacitive coupling between the conductive...
US20140246731 Voids in STI Regions for Forming Bulk FinFETs  
An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void...
US20130277757 Voids in STI Regions for Forming Bulk FinFETs  
An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip...
US20130328132 POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR  
A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a...
US20050253201 Semiconductor device and method of manufacture thereof  
This invention aims at providing an inexpensive semiconductor device having a parasitic diode and lowering the hfe of a parasitic PNP transistor and a manufacture method thereof. Such...
US20100182078 METHODS AND APPARATUS FOR REDUCING COUPLING IN A MOS DEVICE  
Mutual capacitances between regions of a MOS device become substantial factors that limit the speed and performance of the device as the device dimensions are reduced in size. A MOS transistor...
US20170125539 ETCH STOP FOR AIRGAP PROTECTION  
A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The...
US20170047398 ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF  
The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate...
US20170025413 TRANSISTORS HAVING OFFSET CONTACTS FOR REDUCED OFF CAPACITANCE  
Systems, apparatuses and methods for reduced OFF capacitance in switching devices are disclosed. A transistor stack includes first and second doped regions serving as a source and drain,...
US20170012120 STRUCTURE TO ENABLE TITANIUM CONTACT LINER ON pFET SOURCE/DRAIN REGIONS  
A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each...
US20160380065 SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)  
Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The...
US20160329320 POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR  
A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a...
US20160329251 UNIDIRECTIONAL SPACER IN TRENCH SILICIDE  
A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing minor sides of the trench region include...
US20160268158 AIR GAP CONTACT FORMATION FOR REDUCING PARASITIC CAPACITANCE  
A functional gate structure is located on a surface of a semiconductor material portion and including a U-shaped gate dielectric portion and a gate conductor portion. A source region is located on...
US20160233207 SEMICONDUCTOR DEVICE  
In the semiconductor device including the off transistor serving as an ESD protection element and an output element between a first external connection terminal and a second external connection...
US20160141379 INTEGRATED CIRCUITS WITH MIDDLE OF LINE CAPACITANCE REDUCTION IN SELF-ALIGNED CONTACT PROCESS FLOW AND FABRICATION METHODS  
Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for...
US20160133693 SEMICONDUCTOR DEVICE HAVING A METAL GATE  
A semiconductor device comprises a non-conductive gate feature over a substrate, and a metal gate electrode over the substrate. The metal gate electrode comprises a portion over an active region...
US20160118462 FinFET with an Asymmetric Source/Drain Structure and Method of Making Same  
Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor...
US20160099260 DISPLAY PANEL  
A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The...
US20160079354 INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME  
An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active...
US20160064501 UNDER-SPACER DOPING IN FIN-BASED SEMICONDUCTOR DEVICES  
A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin including a channel region of the...
US20160056279 SEMICONDUCTOR DEVICE  
A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of a bottom part of the pillar-shaped silicon layer is...
US20160018693 ARRAY SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR DRIVING DISPLAY DEVICE  
According to the array substrate provided by this disclosure, in a row of sub-pixels, sub-pixels in the odd columns and even columns are separately coupled to different gate lines, i.e., making...
US20160005729 RADIO FREQUENCY TRANSISTOR STACK WITH IMPROVED LINEARITY  
A RF transistor stack is described. The RF transistor stack comprises a first transistor having a T-gate layout configuration. The first transistor has a body region; a plurality of drain regions;...
US20150303219 DISPLAY APPARATUS  
A liquid crystal display device includes: a TFT substrate that includes gate lines; and a driver circuit section that includes a gate driver that is connected to the gate lines. A frame region...
US20150294861 PRODUCTION METHOD FOR ACTIVE ELEMENT SUBSTRATE, ACTIVE ELEMENT SUBSTRATE, AND DISPLAY DEVICE  
The present invention provides a method of manufacturing an active element substrate aimed at reducing the production costs of an interlayer insulating film made from a spin-on glass material, for...
US20150287796 REDUCED PARASITIC CAPACITANCE WITH SLOTTED CONTACT  
A FET device fabricated by providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate. A second conductor is provided...
US20150279914 DISPLAY PANEL, DISPLAY APPARATUS AND METHOD FOR MANUFACTURING DISPLAY PANEL  
A display panel comprising a first array substrate and a second array substrate assembled with each other, wherein the first array substrate comprises a plurality of first pixel units arranged in...
US20150270263 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device and a method of manufacturing the same are disclosed. In one aspect, the method includes forming a first semiconductor layer and a second semiconductor layer sequentially on...
US20150228660 SEMICONDUCTOR DEVICES HAVING AIRGAPS AND METHODS OF MANUFACTURING THE SAME  
Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate...
US20150179658 Semiconductor Memory Devices and Manufacturing Methods Thereof  
A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a...
US20140167178 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR  
A semiconductor device includes a non-conductive gate feature over a substrate and a spacer adjoining each sidewall of the non-conductive gate feature.
US20110193175 LOWER PARASITIC CAPACITANCE FINFET  
An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a...

Matches 1 - 42 out of 42