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US20140183652 DUMMY METAL GATE STRUCTURES TO REDUCE DISHING DURING CHEMICAL-MECHANICAL POLISHING  
The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical...
US20120228715 ENGINEERED OXYGEN PROFILE IN METAL GATE ELECTRODE AND NITRIDED HIGH-K GATE DIELECTRICS STRUCTURE FOR HIGH PERFORMANCE PMOS DEVICES  
A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low...
US20120241868 METAL-GATE CMOS DEVICE  
A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are...
US20140183653 HIGH-K METAL GATE  
An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a...
US20110303984 Quadrangle MOS Transistors  
A quadrangle transistor unit includes four transistor units. Each of the four transistor units includes a gate electrode. The gate electrodes of the four transistor units are aligned to four sides...
US20150187771 HYBRID HIGH-K FIRST AND HIGH-K LAST REPLACEMENT GATE PROCESS  
An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor...
US20140131809 REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE  
A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an...
US20120261765 HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING  
In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal...
US20110127613 HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING  
In a replacement gate approach in sophisticated semiconductor devices, the place-holder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal...
US20110254098 INTEGRATED CIRCUIT WITH REPLACEMENT METAL GATES AND DUAL DIELECTRICS  
A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated...
US20140306291 Dual Silicide Process Compatible with Replacement-Metal-Gate  
In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined...
US20140306290 Dual Silicide Process Compatible with Replacement-Metal-Gate  
In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined...
US20120043618 Performance-Aware Logic Operations for Generating Masks  
Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from...
US20130187239 STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY  
A complementary metal oxide semiconductor structure including a scaled nFET and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided....
US20130249014 DUMMY GATE CELL, CELL-BASED IC, LAYOUT SYSTEM AND LAYOUT METHOD OF CELL-BASED IC, AND PORTABLE DEVICE  
A dummy gate cell includes an nMOS transistor and a pMOS transistor which constitute a CMOS inverter, wherein a drain electrode of the nMOS transistor and a drain electrode of the pMOS transistor...
US20120292710 METHOD FOR SELF-ALIGNED METAL GATE CMOS  
A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of...
US20110147837 DUAL WORK FUNCTION GATE STRUCTURES  
A semiconductor chip having a transistor is described. The transistor having a gate electrode disposed over a gate dielectric. The gate electrode comprised of first gate material disposed on the...
US20110115028 Inducing Strain in the Channels of Metal Gate Transistors  
In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than...
US20130154021 ENHANCED GATE REPLACEMENT PROCESS FOR HIGH-K METAL GATE TECHNOLOGY  
The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is formed over a portion of the high-k...
US20150069516 INNER L-SPACER FOR REPLACEMENT GATE FLOW  
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a...
US20150048457 Mask Optimization for Multi-Layer Contacts  
A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated...
US20140191326 PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE  
A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the...
US20120037999 DIFFERENTIAL STOICHIOMETRIES BY INFUSION THRU GCIB FOR MULTIPLE WORK FUNCTION METAL GATE CMOS  
A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although...
US20120018810 Structure And Method For Dual Work Function Metal Gate CMOS With Selective Capping  
A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode...
US20110175168 NMOS TRANSISTOR WITH ENHANCED STRESS GATE  
A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type...
US20150187938 LOW COST DEMOS TRANSISTOR WITH IMPROVED CHC IMMUNITY  
An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance...
US20100308412 CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES  
A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than...
US20090014807 DUAL STRESS LINERS FOR INTEGRATED CIRCUITS  
Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for...
US20110147851 Method For Depositing Gate Metal For CMOS Devices  
A semiconductor device comprises a substrate, a channel region, and a gate formed in association with the channel region. In one exemplary embodiment, the gate comprises a first material that is...
US20150228749 ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES  
A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed...
US20150035073 ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES  
A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed...
US20150194350 THRESHOLD VOLTAGE TUNING USING SELF-ALIGNED CONTACT CAP  
Methods of forming a PFET dielectric cap with varying concentrations of H2 reactive gas and the resulting devices are disclosed. Embodiments include forming p-type and n-type metal gate stacks,...
US20140346609 CMOS Process To Improve SRAM Yield  
An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that...
US20120104510 CMOS PROCESS TO IMPROVE SRAM YIELD  
An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that...
US20140131808 REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE  
A method of fabricating a replacement metal gate structure for a CMOS device. The method includes forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device;...
US20110049640 SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER  
In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed...
US20150035074 FINFET DEVICES INCLUDING RECESSED SOURCE/DRAIN REGIONS HAVING OPTIMIZED DEPTHS AND METHODS OF FORMING THE SAME  
A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain...
US20130299915 DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS  
Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure...
US20130001701 Vertical Stacking of Field Effect Transistor Structures for Logic Gates  
Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in...
US20110248349 Vertical Stacking of Field Effect Transistor Structures for Logic Gates  
Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in...
US20150054087 REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE  
A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled...
US20150035078 METAL GATE TRANSISTOR AND INTEGRATED CIRCUITS  
A transistor includes a gate dielectric structure over a substrate and a work function metallic layer over the gate dielectric structure. The work function metallic layer is configured to adjust a...
US20080029823 Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress Liner  
In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on...
US20110006372 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES  
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are...
US20130193523 STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET  
An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure....
US20110175170 STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET  
An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure....
US20120181616 STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY  
A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an...
US20090090974 DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD  
A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile...
US20150102417 DOUBLE TRENCH WELL FORMATION IN SRAM CELLS  
A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each...
US20140151813 COMPUTER CHIP ARCHITECTURE  
A computer chip utilizing a hybrid metal gate wherein metal inserted poly silicon (MIPS) is used for nMOS and replacement metal gate (RMG) is used for pMOS, and wherein poly silicon doping over...