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US20140084374 CELL DESIGN  
One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down...
US20120280323 DEVICE HAVING A GATE STACK  
A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a...
US20120319205 HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY REDUCING A GATE FILL ASPECT RATIO IN REPLACEMENT GATE TECHNOLOGY  
When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as...
US20120001263 Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric  
In replacement gate approaches for forming sophisticated high-k metal gate electrode structures in a late manufacturing stage, the exposing of the placeholder material may be accomplished on the...
US20140252487 Gate Security Feature  
An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit...
US20150035568 TEMPERATURE DETECTOR AND CONTROLLING HEAT  
A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close...
US20130168773 High-K Metal Gate Electrode Structure Formed by Removing a Work Function on Sidewalls in Replacement Gate Technology  
When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as...
US20150076613 OVERLAY MARK  
An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in a second longitudinal direction. The...
US20130292772 LAYOUT DESIGNS WITH VIA ROUTING STRUCTURES  
An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact...
US20120080755 Methods for Forming Gates in Gate-Last Processes and Gate Areas formed by the Same  
Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of...
US20150187758 SCHOTTKY DIODES FOR REPLACEMENT METAL GATE INTEGRATED CIRCUITS  
An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.
US20110095371 Gate minimization threshold voltage of FET for synchronous rectification  
A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be...
US20130075820 Superior Integrity of High-K Metal Gate Stacks by Forming STI Regions After Gate Metals  
When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in...
US20110266626 GATE DEPLETION DRAIN EXTENDED MOS TRANSISTOR  
A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and...
US20140021552 Strain Adjustment in the Formation of MOS Devices  
A method includes forming a gate stack over a semiconductor substrate, and forming a gate spacer on a sidewall of the gate stack. After the step of forming the gate spacer, the gate spacer is...
US20140103443 SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF  
A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate...
US20130146985 TRENCH ISOLATION STRUCTURE  
A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and...
US20130069160 TRENCH ISOLATION STRUCTURE  
A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and...
US20130087857 NITROGEN PASSIVATION OF SOURCE AND DRAIN RECESSES  
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the...
US20130234253 SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES  
A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between...
US20150048457 Mask Optimization for Multi-Layer Contacts  
A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated...
US20130270644 REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING  
Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further...
US20130299904 LDMOS One-Time Programmable Device  
According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a...
US20150035066 FET CHIP  
An FET chip is configured to include an oscillation suppression circuit that has a gate capacitance C formed between a gate electrode 5c and two-dimensional electron gas, and a channel resistance...
US20110133286 INTEGRIERTER SCHALTUNGSTEIL  
An integrated circuit part containing at least one MOS transistor with a trace system, with a source region having a source contact, and with a drain region having a drain contact, and with a gate...
US20130292773 CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES  
An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a...
US20120223388 SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER  
In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed...
US20140063744 Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance  
A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge...
US20120139051 SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS  
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate...
US20130181293 DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR  
A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a...
US20110248347 LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS  
An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D...
US20130320449 LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS  
A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side...
US20150221639 DIGITAL CIRCUIT DESIGN WITH SEMI-CONTINUOUS DIFFUSION STANDARD CELL  
A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second...
US20120092925 VERTICAL CAPACITOR-LESS DRAM CELL, DRAM ARRAY AND OPERATION OF THE SAME  
A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an...
US20130119473 GATE STRUCTURES AND METHODS OF MANUFACTURE  
A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes...
US20110147850 CARBON AND NITROGEN DOPING FOR SELECTED PMOS TRANSISTORS ON AN INTEGRATED CIRCUIT  
A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core...
US20110012205 METHOD FOR FABRICATING A METAL GATE STRUCTURE  
A metal gate structure is disclosed. The metal gate structure includes: a semiconductor substrate having an active region and an isolation region; an isolation structure disposed in the isolation...
US20150021693 ENHANCING TRANSISTOR PERFORMANCE AND RELIABILITY BY INCORPORATING DEUTERIUM INTO A STRAINED CAPPING LAYER  
When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the...
US20140097498 Open Source Power Quad Flat No-Lead (PQFN) Leadframe  
According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase...
US20150235948 GROUNDING DUMMY GATE IN SCALED LAYOUT DESIGN  
A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact,...
US20080122001 INTEGRATED CIRCUIT HAVING DOPED SEMICONDUCTOR BODY AND METHOD  
An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects...
US20130320450 MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS  
A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions...
US20140332893 Integrated Circuit Device Having Defined Gate Spacing And Method Of Designing And Fabricating Thereof  
A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate...
US20130032884 INTEGRATED CIRCUIT DEVICE HAVING DEFINED GATE SPACING AND METHOD OF DESIGNING AND FABRICATING THEREOF  
A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate...
US20140070320 INTEGRATED CIRCUITS WITH SELECTIVE GATE ELECTRODE RECESS  
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain...
US20140042548 DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF  
A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and...
US20120061764 MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE  
The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such...
US20110095375 MIM TRANSISTOR  
The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.
US20130307081 GATE STACK WITH ELECTRICAL SHUNT IN END PORTION OF GATE STACK  
A semiconductor device is formed in which a first-type doped field effect transistor has a first gate stack that has an end portion with a second gate stack formed for a second-type, complementary...
US20140327081 STANDARD CELL METAL STRUCTURE DIRECTLY OVER POLYSILICON STRUCTURE  
A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a...