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US20090121283 Semiconductor device and fabrication method of the same  
A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower...
US20170186866 VERTICAL FIELD EFFECT TRANSISTOR HAVING A DISC SHAPED GATE  
A vertical FET, including a source layer, a channel layer, a drain layer and a gate dielectric, the source layer being coupled with a source electrode, the channel layer being deposited on top of...
US20170186742 IMPLEMENTATION OF LONG-CHANNEL THICK-OXIDE DEVICES IN VERTICAL TRANSISTOR FLOW  
A method for fabricating a semiconductor structure is provided that includes the steps of: forming a structure including a substrate, a counter-doped layer on the substrate, and a heavily doped...
US20170179302 VERTICAL FIELD EFFECT TRANSISTORS  
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with...
US20170179282 CHANNEL-LAST REPLACEMENT METAL-GATE VERTICAL FIELD EFFECT TRANSISTOR  
A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench in the sacrificial gate material to...
US20170179281 Self-Aligned Nanostructures for Semiconductor Devices  
A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a...
US20170179276 SUPER-JUNCTION SEMICONDUCTOR DEVICE  
A super-junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer, a field insulator, a floating electrode layer, an isolation layer,...
US20170179259 VERTICAL TRANSISTOR FABRICATION AND DEVICES  
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess;...
US20170179134 LAYOUT OF STATIC RANDOM ACCESS MEMORY CELL  
A static random access memory (SRAM) cell is defined by first and second boundaries disposed opposite to each other and third and fourth boundaries disposed opposite to each other and intersected...
US20170179116 INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET  
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a...
US20170178974 VERTICAL FETS WITH VARIABLE BOTTOM SPACER RECESS  
A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second...
US20170178970 VARIABLE GATE LENGTHS FOR VERTICAL TRANSISTORS  
The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method...
US20170170313 Method of Producing a Pre-Patterned Structure for Growing Vertical Nanostructures  
A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure...
US20170170196 HYBRID CIRCUIT INCLUDING A TUNNEL FIELD-EFFECT TRANSISTOR  
The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a...
US20170162559 INTEGRATED VERTICAL SHARP TRANSISTOR AND FABRICATION METHOD THEREOF  
The present invention relates to vertical integrated, quantized FET with sharp drain and BJT with sharp emitter implemented in one nano-BiCMOS process, using multiple identical single crystalline...
US20170162446 MULTIPLE GATE LENGTH VERTICAL FIELD-EFFECT-TRANSISTORS  
Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact...
US20170154994 METHODS OF FORMING A CONTACT STRUCTURE FOR A VERTICAL CHANNEL SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE  
One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the...
US20170154992 Transistor Device with Increased Gate-Drain Capacitance  
Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode...
US20170154856 Chip Protection Envelope and Method  
In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die...
US20170154807 Vertical Structure and Method of Forming Semiconductor Device  
According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over...
US20170148913 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A semiconductor device includes a pillar-shaped semiconductor layer and a first gate insulating film around the pillar-shaped semiconductor layer. A metal gate electrode is around the first gate...
US20170148910 TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE  
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an...
US20170148872 Field-Effect Semiconductor Device Having Pillar Regions of Different Conductivity Type Arranged in an Active Area  
In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain...
US20170148871 MOSFET HAVING DUAL-GATE CELLS WITH AN INTEGRATED CHANNEL DIODE  
A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active...
US20170148870 POWER SEMICONDUCTOR DEVICE  
A power semiconductor device includes a substrate, a main body, and an electrode unit. The main body includes an active portion disposed on the substrate, an edge termination portion, and an...
US20170148711 SEMICONDUCTOR PACKAGE  
Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a...
US20170141191 PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE  
Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the...
US20170133513 METHOD TO MAKE SELF-ALIGNED VERTICAL FIELD EFFECT TRANSISTOR  
A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and...
US20170133230 SEMICONDUCTOR DEVICE HAVING VERTICAL SILICON PILLAR TRANSISTOR  
A semiconductor device includes a transistor disposed on a substrate, a first insulation layer, a second insulation layer, an epitaxy and a conductive material. The first insulation layer is...
US20170125585 Field-Effect Transistor With Dual Vertical Gates  
A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a...
US20170125580 Latch-Up Resistant Transistor  
Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a...
US20170125518 Elongated Semiconductor Structure Planarization  
According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor...
US20170125345 Semiconductor Chip with Integrated Series Resistances  
A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift...
US20170125344 SEMICONDUCTOR DEVICE  
A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer formed on the interconnection layer, a...
US20170117377 Semiconductor Structures and Methods for Multi-Level Work Function  
Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a...
US20170117271 THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding...
US20170110322 Semiconductor Device and Methods for Forming a Semiconductor Device  
A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and...
US20170098706 Field Effect Transistors and Methods of Forming Same  
Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second...
US20170092778 GATE ALL AROUND VACUUM CHANNEL TRANSISTOR  
A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing...
US20170092761 SEMICONDUCTOR DEVICE  
A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of...
US20170092717 Superjunction Semiconductor Device with Oppositely Doped Semiconductor Regions Formed in Trenches and Method of Manufacturing  
A trench etch mask is formed on a process surface of a semiconductor layer. By using the trench etch mask, both first trenches and second trenches are formed that extend from the process surface...
US20170092632 MEMORY STRUCTURE  
A memory structure is provided. The memory structure includes a first chip. The first chip has an array region and a periphery region. The first chip includes a first stack and a plurality of...
US20170084753 Top Metal Pads as Local Interconnectors of Vertical Transistors  
An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top...
US20170084740 3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME  
A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is...
US20170084691 SEMICONDUCTOR DEVICE HAVING VERTICAL SEMICONDUCTOR PILLARS  
A semiconductor device includes a plurality of substantially vertical semiconductor pillars on a substrate, and a hard mask layer overlying the plurality of semiconductor pillars. A contiguous...
US20170077265 SEMICONDUCTOR DEVICE  
A semiconductor device includes a fin-shaped semiconductor layer and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal gate line is connected to a metal gate...
US20170077253 Contacts for Highly Scaled Transistors  
A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(S/D) regions, a channel between the first and...
US20170077068 SEMICONDUCTOR DEVICE  
A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source...
US20170069758 VERTICAL NON-PLANAR SEMICONDUCTOR DEVICE FOR SYSTEM-ON-CHIP (SOC) APPLICATIONS  
Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor...
US20170069650 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a semiconductor film extending in stacking direction of...