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US20140225184 Method for Inducing Strain in Vertical Semiconductor Columns  
A vertical Metal-Oxide-Semiconductor (MOS) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material. An oxide ring extends from an outer...
US20100013007 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device (10) of the present invention includes: a drift layer (5) that includes a reference concentration layer (4) including an impurity of a first conductive type at a first...
US20140252457 MULTI-LANDING CONTACT ETCHING  
A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a...
US20120292687 SUPER JUNCTION TRANSISTOR AND FABRICATION METHOD THEREOF  
A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the...
US20090166672 Sawtooth electric field drift region structure for power semiconductor devices  
This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of...
US20120080742 Semiconductor device having vertical type transistor  
A semiconductor device includes: a first vertical type transistor having a first lower diffusion layer, a first upper diffusion layer, and a gate electrode; a second vertical type transistor...
US20150236086 SEMICONDUCTOR STRUCTURES AND METHODS FOR MULTI-LEVEL WORK FUNCTION  
A semiconductor structure is provided comprising a vertical channel structure extending from a substrate and formed as a channel between a source region and a drain region. The semiconductor...
US20100025758 METHOD OF MANUFACTURING HIGH-INTEGRATED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME  
A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a...
US20140264558 FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS  
A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a...
US20060108635 Trenched MOSFETS with part of the device formed on a (110) crystal plane  
This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is...
US20150069500 VERTICAL TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF  
A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one...
US20140010007 ELECTRONIC DEVICE AND METHOD FOR FORMING THE SAME  
An electronic device includes a device isolation film formed to define an active region in a substrate, a first gate buried to traverse the active region and the device isolation film in a first...
US20090236656 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an...
US20080258209 SEMICONDUCTOR DEVICE AND MANUFATURING METHOD THEREOF  
A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending...
US20150228659 DATA LINE ARRANGEMENT AND PILLAR ARRANGEMENT IN APPARATUSES  
Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar...
US20140327070 Super Junction Structure Semiconductor Device Based on a Compensation Structure Including Compensation Layers and a Fill Structure  
A super junction semiconductor device includes strip structures between mesa regions that protrude from a base section in a cell area. Each strip structure includes a compensation structure with a...
US20130153993 HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE  
A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a FINFET device on the same SOI...
US20140027838 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
According to one embodiment, the stair array includes a deep portion, one stair, and a plurality of stairs. The one stair is provided next to the deepest portion in the first direction and has a...
US20120273871 Superjunction Structures for Power Devices and Methods of Manufacture  
A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second...
US20100090273 TRANSISTOR STRUCTURE HAVING DUAL SHIELD LAYERS  
A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and...
US20120061747 SEMICONDUCTOR DEVICE  
According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity...
US20110241104 INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION  
An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel...
US20090159964 VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME  
A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is...
US20070145474 VERTICAL-GATE MOS TRANSISTOR FOR HIGH VOLTAGE APPLICATIONS WITH DIFFERENTIATED OXIDE THICKNESS  
A vertical-gate MOS transistor is integrated in a semiconductor chip of a first conductivity type having a main surface, and includes an insulated trench gate extending into the semiconductor chip...
US20140197476 SEMICONDUCTOR DEVICE  
A semiconductor device includes element active portion X and element peripheral portion Y. An interlayer insulating film is formed on upper surfaces of portions X and Y. A source electrode...
US20140021533 SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR  
A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a...
US20090294842 METHODS OF FORMING DATA CELLS AND CONNECTIONS TO DATA CELLS  
Disclosed are methods and devices, among which is a method that includes forming a lower conductive material on a substrate, forming a stop material on the substrate, forming a sacrificial...
US20140015036 TRENCHED AND IMPLANTED ACCUMULATION MODE METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR  
The present invention provides AccuFETs with single or dual accumulation channels and methods for manufacturing the same. The present invention also provides for products produced by the methods...
US20140001540 INTEGRATED SEMICONDUCTOR DEVICE AND FABRICATION METHOD  
A method is provided for fabricating an integrated semiconductor device. The method includes providing a semiconductor substrate having a first active region, a second active region and a...
US20110284949 VERTICAL TRANSISTOR AND A METHOD OF FABRICATING THE SAME  
A vertical transistor and a method of fabricating the vertical transistor are provided. The vertical transistor has a substrate, a first electrode formed on the substrate, a first insulation layer...
US20150171210 Electronic Device Including a Vertical Conductive Structure  
An electronic device can include a buried conductive region and a semiconductor layer over the buried conductive region. The electronic device can further include a horizontally-oriented doped...
US20120126312 VERTICAL DMOS-FIELD EFFECT TRANSISTOR  
A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), has a cell structure with a substrate; an epitaxial layer or well of the first conductivity type on the...
US20100258857 Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor  
This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon...
US20080157189 Power Semiconductor Device  
Disclosed is a power semiconductor device capable of transmitting a gate signal from any upward, downward, leftward, and rightward directions on a plane to reduce deviation in the gate signal's...
US20140225185 METHOD OF MAKING A LOW-RDSON VERTICAL POWER MOSFET DEVICE  
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson...
US20130049100 METHOD OF MAKING A LOW-RDSON VERTICAL POWER MOSFET DEVICE  
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson...
US20120126314 VERTICAL DMOS-FIELD EFFECT TRANSISTOR  
A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first...
US20060097313 Semiconductor device and method of manufacturing same  
A semiconductor device comprises a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type provided on a major surface of the...
US20150162261 Power Semiconductor Package with Integrated Heat Spreader and Partially Etched Conductive Carrier  
In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top...
US20080173936 ACCESS DEVICE HAVING VERTICAL CHANNEL AND RELATED SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE ACCESS DEVICE  
An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate...
US20060097312 Method for producing a vertical transistor component  
The invention relates to a method for producing a vertical transistor component, having the following method steps of: Providing a semiconductor substrate (100), applying an auxiliary layer (110)...
US20060065925 Vertical MOSFET  
A vertical MOSFET includes a gate electrode formed inside a trench in a semiconductor layer, an interlayer insulating film formed above the semiconductor layer, a source electrode formed above the...
US20110175161 Advanced Forming Method and Structure of Local Mechanical Strained Transistor  
Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor...
US20100078698 Vertical semiconductor device, dram device including the same  
A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a...
US20090039420 FINFET MEMORY CELL HAVING A FLOATING GATE AND METHOD THEREFOR  
A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure...
US20080029809 Semiconductor device having a vertical transistor structure  
A semiconductor device includes a semiconductor substrate having a semiconductor layer on a major surface thereof. The semiconductor layer is formed to extend in the vertical direction of the...
US20080179664 SEMICONDUCTOR DEVICE WITH A VERTICAL MOSFET INCLUDING A SUPERLATTICE AND RELATED METHODS  
A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice...
US20150108560 VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY  
Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines...
US20130228854 POWER FIELD EFFECT TRANSISTOR  
A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type...
US20100219463 QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE  
A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over...