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US20110101448 VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF  
A vertical transistor includes: a substrate, a bottom-oxide layer, an epitaxial silicon layer, an insulating oxide layer, two gate-oxide films and a gate-stacked layer. The bottom-oxide layer is...
US20150001614 SEMICONDUCTOR DEVICE HAVING A SURROUND GATE TRANSISTOR  
A semiconductor device includes a first-conductive type first pillar, a first dielectric surrounding the first pillar, a gate surrounding the dielectric, a second pillar underneath the first...
US20110169074 VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME  
A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is...
US20120126310 METHOD FOR FORMING CHANNEL MATERIAL  
The present invention provides a method for forming a channel material, comprising: forming a substrate; forming an MOS device with a dummy gate stack on the substrate; removing the dummy gate...
US20140159140 BURIED WORD LINE STRUCTURE AND METHOD OF FORMING THE SAME  
A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a...
US20110024828 SEMICONDUCTOR STORAGE DEVICE  
An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together,...
US20150084118 SEMICONDUCTOR DEVICE INCLUDING A POWER TRANSISTOR DEVICE AND BYPASS DIODE  
A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the...
US20140203350 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same  
A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is...
US20120306003 TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS  
Disclosed is a MOSFET including at least one transistor cell. The at least one transistor cell includes a source region, a drain region, a body region and a drift region. The body region is...
US20100109077 High-voltage vertical transistor with a multi-gradient drain doping profile  
A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second...
US20140070306 VERTICAL MEMORY DEVICES AND APPARATUSES  
Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally...
US20130161732 VERTICAL CHANNEL THIN FILM TRANSISTOR  
Disclosed is a vertical channel thin film transistor including a substrate; a drain electrode formed on the substrate; a spacer formed on the substrate while coming into contact with the drain...
US20110241103 METHOD OF MANUFACTURING A TUNNEL TRANSISTOR AND IC COMPRISING THE SAME  
A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the...
US20050167745 Semiconductor device with element isolation region and method of fabricating the same  
A semiconductor device includes a semiconductor substrate having an upper face, a plurality of trenches formed in the semiconductor substrate, an element isolating film embedded in each trench and...
US20150054065 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same  
A method of making a tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate....
US20110210783 TRANSISTOR INCLUDING REENTRANT PROFILE  
A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically...
US20070246763 TRENCH STEP CHANNEL CELL TRANSISTOR AND MANUFACTURE METHOD THEREOF  
A trench step channel cell transistor and a manufacture method thereof are disclosed. The transistor could be applied to increase the channel length thereof. The transistor comprises a step...
US20130341707 SEMICONDUCTOR DEVICE  
A semiconductor device includes a first pillar, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region...
US20100090272 TRANSISTOR STRUCTURE HAVING A CONDUCTIVE LAYER FORMED CONTIGUOUS IN A SINGLE DEPOSITION  
A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying...
US20090315102 Process and system for manufacturing a MOS device with intercell ion implant  
A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region (25), above the...
US20080173937 SEMICONDUCTOR MEMORY DEVICES INCLUDING VERTICALLY ORIENTED TRANSISTORS AND METHODS OF MANUFACTURING SUCH DEVICES  
A semiconductor device includes a first active pattern including an upper portion and a lower portion formed on a substrate, a second active pattern formed on the first active pattern, and a gate...
US20150221731 VERTICAL POWER MOSFET HAVING PLANAR CHANNEL AND ITS METHOD OF FABRICATION  
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant...
US20150200290 PLANAR MOSFETS AND METHODS OF FABRICATION, CHARGE RETENTION  
A planar MOSFET includes a plurality of MOSFET cells. Each MOSFET cell includes an epitaxial layer of a first conductivity type, a body region of a second conductivity type inside the epitaxial...
US20090166725 VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME  
A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and...
US20140167146 TUNNELING FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF  
A tunneling field effect transistor (FET) and a method of fabricating the same are provided. The tunneling FET includes a first electrode formed on a substrate, a second electrode disposed over...
US20080006908 Body-tied, strained-channel multi-gate device and methods of manufacturing same  
A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor...
US20130082321 DUAL-GATE VDMOS DEVICE  
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second...
US20080224205 Vertical Thin-Film Transistor with Enhanced Gate Oxide  
A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical...
US20090302346 MOS TYPE SEMICONDUCTOR DEVICE  
A surface between gate electrodes in an MOS gate structure is patterned so that missing portions are partially provided in surfaces of n+ emitter regions to thereby enlarge surface areas of p+...
US20060261406 Vertical integrated-gate CMOS device and its fabrication process  
A vertical integrated-gate CMOS (Complementary Metal-Oxide-Silicon field effect transistor) device is invented for the first time and its possible fabrication processes are proposed. This CMOS...
US20130168759 FIELD EFFECT TRANSISTOR WITH A VERTICAL CHANNEL AND FABRICATION METHOD THEREOF  
Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which...
US20070210374 VERTICAL-TYPE SURROUNDING GATE SEMICONDUCTOR DEVICE  
A vertical-type surrounding gate semiconductor device is described. The semiconductor device comprises a pillar substrate, a collar oxide layer, a metal layer, a drain region, a ground line, a...
US20150214350 MOS-Gated Power Devices, Methods, and Integrated Circuits  
MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate...
US20130093001 POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS  
This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface....
US20120280308 VERTICAL POWER TRANSISTOR DIE PACKAGES AND ASSOCIATED METHODS OF MANUFACTURING  
The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the...
US20150228759 VERTICAL DEVICE AND METHOD OF FORMING THE SAME  
According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a...
US20130009169 METHODS OF MAKING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITHOUT ION IMPLANTATION AND DEVICES MADE THEREWITH  
Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion...
US20100320530 METHODS OF MAKING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITHOUT ION IMPLANTATION AND DEVICES MADE THEREWITH  
Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion...
US20080303083 SEMICONDUCTOR APPARATUS AND PRODUCTION METHOD OF THE SAME  
In order to provide a highly integrated semiconductor apparatus and a production method thereof which can avoid the floating of a channel portion that causes a problem when constituting a memory...
US20120280309 MOS TRANSISTOR SUPPRESSING SHORT CHANNEL EFFECT AND METHOD OF FABRICATING THE SAME  
A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion...
US20120032255 INTEGRATED CIRCUIT HAVING COMPENSATION COMPONENT  
An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order...
US20090121268 Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods  
A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar...
US20120256253 Vertical Memory Devices  
Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a...
US20150206898 PARALLELOGRAM CELL DESIGN FOR HIGH SPEED VERTICAL CHANNEL 3D NAND MEMORY  
Roughly described, a memory device has a multilevel stack of conductive layers. Pillars oriented orthogonally to the substrate each include series-connected memory cells at cross-points between...
US20150014765 RADIATION RESISTANT CMOS DEVICE AND METHOD FOR FABRICATING THE SAME  
A radiation resistant CMOS device and a method for fabricating the same. The CMOS device includes a substrate, a source region, a drain region and a vertical channel on the substrate. A first...
US20140327069 Semiconductor Device with a Super Junction Structure Based On a Compensation Structure with Compensation Layers and Having a Compensation Rate Gradient  
A super junction structure is formed in a semiconductor portion of a super junction semiconductor device. The super junction structure includes a compensation structure with a first compensation...
US20120241831 Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, and DRAM Cells  
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking...
US20110140187 Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, And DRAM Cells  
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking...
US20100078712 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device includes a first semiconductor pillar, a first gate insulating film, a gate electrode, and a first contact. The first semiconductor pillar extends upwardly from a...
US20090159927 INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION  
An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel...