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US20120319192 Gate Structures  
An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel...
US20100200912 Mosfets with terrace irench gate and improved source-body contact  
A trench MOSFET with terrace gates and improved source-body contact structure is disclosed. When refilling the gate trenches, the deposited polysilicon layer is higher than the sidewalls of the...
US20090085102 SEMICONDUCTOR DEVICE HAVING VERTICAL SURROUNDING GATE TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM  
A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a...
US20120228696 STACKED DIE POWER CONVERTER  
A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor)...
US20110089482 METHOD AND APPARATUS FOR CONTROLLING A CIRCUIT WITH A HIGH VOLTAGE SENSE DEVICE  
A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first...
US20110175160 SHORT-CHANNEL SCHOTTKY-BARRIER MOSFET DEVICE AND METHOD OF MANUFACTURE  
A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device...
US20100090668 Stacked Field Effect Transistor Configurations  
An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain...
US20130093000 VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE  
A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled...
US20090152623 FIN TRANSISTOR  
A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress...
US20150123194 Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Transistor  
A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDSON) of the device. The DSV plugs extend through a...
US20120007176 High-Voltage Bipolar Transistor with Trench Field Plate  
A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial...
US20100237847 POWER SUPPLY CIRCUIT  
A power supply circuit has a first MOSFET having a body region between the source and drain. The body region is connected so as to be at the same potential as the source. Application of a suitable...
US20120256254 STRUCTURE AND FABRICATION PROCESS OF SUPER JUNCTION MOSFET  
This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a...
US20130037852 POWER MOSFET, AN IGBT, AND A POWER DIODE  
Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when...
US20150187935 SEMICONDUCTOR DEVICE INCLUDING PILLAR TRANSISTORS  
A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a...
US20130082323 SUPERJUNCTION STRUCTURE, SUPERJUNCTION MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF  
A superjunction structure with unevenly doped P-type pillars (4) and N-type pillars (2a) is disclosed. The N-type pillars (2a) have uneven impurity concentrations in the vertical direction and the...
US20150179655 STATIC RANDOM ACCESS MEMORY (SRAM) CELLS INCLUDING VERTICAL CHANNEL TRANSISTORS AND METHODS OF FORMING THE SAME  
A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access...
US20150162431 PLANAR VERTICAL DMOS TRANSISTOR WITH REDUCED GATE CHARGE  
A planar vertical DMOS transistor includes a dielectric separation structure formed under the conductive gate and over the bulk of the semiconductor layer outside of the channel region of the...
US20110204435 VERTICAL CAPACITIVE DEPLETION FIELD EFFECT TRANSISTOR  
Vertical capacitive depletion field effect transistors (VCDFETs) and methods for fabricating VCDFETs are disclosed. An example VCDFET includes one or more interleaved drift and gate regions. The...
US20090078971 SEMICONDUCTOR DEVICE WITH STRUCTURED CURRENT SPREAD REGION AND METHOD  
A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first...
US20090302377 VERTICAL-TYPE SEMICONDUCTOR DEVICE  
In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor...
US20140183622 SCHOTTKY POWER MOSFET  
A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power...
US20140203351 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same  
A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is...
US20130240955 VERTICAL TRANSISTOR HAVING EDGE TERMINATION STRUCTURE  
Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the...
US20130153988 ELECTRONIC DEVICE INCLUDING A TRENCH WITH A FACET AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME  
An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an...
US20130093497 TUNNEL FIELD EFFECT TRANSISTOR (TFET) WITH LATERAL OXIDATION  
A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling...
US20100096691 SEMICONDUCTOR DEVICE HAVING VERTICALLY ALIGNED PILLAR STRUCTURES THAT HAVE FLAT SIDE SURFACES AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate,...
US20140374818 Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same  
A structure of trench VDMOS transistor comprises an n− epi-layer/n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si...
US20150179660 Three Dimensional NAND Device with Channel Located on Three Sides of Lower Select Gate and Method of Making Thereof  
A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side,...
US20090189217 Semiconductor Memory Devices Including a Vertical Channel Transistor  
Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding...
US20140027839 SRAM DEVICES AND METHODS OF MANUFACTURING THE SAME  
Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that...
US20130026559 SILICON-CARBIDE MOSFET CELL STRUCTURE AND METHOD FOR FORMING SAME  
In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the...
US20110062489 POWER DEVICE WITH SELF-ALIGNED SILICIDE CONTACT  
An improved power device with a self-aligned suicide and a method for fabricating the device are disclosed. An example power device is a vertical power device that includes contacts formed on gate...
US20120228698 VERTICAL COMPLEMENTARY FET  
A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit....
US20150084119 LAYOUT CONFIGURATIONS FOR INTEGRATING SCHOTTKY CONTACTS INTO A POWER TRANSISTOR DEVICE  
A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact...
US20130082320 STRAPPED DUAL-GATE VDMOS DEVICE  
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second...
US20110012194 Multi-die DC-DC Buck Power Converter with Efficient Packaging  
A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The...
US20080164515 High-density power MOSFET with planarized metalization  
A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical...
US20140339625 PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE  
A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is...
US20130181280 PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE  
A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is...
US20120126313 ULTRA THIN DIE TO IMPROVE SERIES RESISTANCE OF A FET  
A method for producing a power field effect transistor (FET) device having a low series resistance between the drain and source when switched on has the steps of: forming a vertical power FET in a...
US20110006361 Integrated Power Supplies and Combined High-Side Plus Low-Side Switches  
The present application discloses new approaches to integrated power. Two new classes of structures each provide an integrated phase leg, in a process which can easily be integrated with...
US20100038709 VERTICAL TRANSISTOR AND ARRAY WITH VERTICAL TRANSISTORS  
A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and...
US20070252196 Vertical channel transistors and memory devices including vertical channel transistors  
A semiconductor device is provided which includes an NMOS vertical channel transistor located on a substrate and including a p+ polysilicon gate electrode surrounding a vertical p-channel region,...
US20110233657 High-voltage vertical transistor with a varied width silicon pillar  
In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and...
US20090134456 Semiconductor devices and method of manufacturing them  
The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different...
US20140042525 LATERAL TRANSISTORS AND METHODS WITH LOW-VOLTAGE-DROP SHUNT TO BODY DIODE  
Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one...
US20130146965 METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS  
A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to...
US20110108909 VERTICAL THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE INCLUDING THE VERTICAL THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME  
A vertical thin film transistor and a method for manufacturing the same and a display device including the vertical thin film transistor and a method for manufacturing the same are disclosed. The...
US20130320429 PROCESSES AND STRUCTURES FOR DOPANT PROFILE CONTROL IN EPITAXIAL TRENCH FILL  
Methods of depositing epitaxial material using a repeated deposition and etch process. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is...