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US20160126314 SEMICONDUCTOR DEVICE  
A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source...
US20160126253 Semiconductor Memory Devices Having Increased Distance Between Gate Electrodes and Epitaxial Patterns and Methods of Fabricating the Same  
A semiconductor memory device is provided including a substrate, a plurality of interlayer insulating layers and gate electrodes alternately stacked on the substrate. The plurality of interlayer...
US20160126187 SEMICONDUCTOR DEVICE  
A semiconductor device includes: a semiconductor element having a gate and source electrodes; an insulating substrate which is provided with an insulating plate, a first circuit plate and a second...
US20160118459 CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES  
A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell...
US20160118415 ARRAY SUBSTRATE, DISPLAY PANEL AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR  
An array substrate, a display panel and a method of manufacturing a thin film transistor (TFT) are provided. The array substrate includes a base substrate and a thin film transistor (TFT) formed...
US20160118399 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE  
A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation...
US20160111523 METHOD OF FORMING A VERTICAL DEVICE  
According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the...
US20160104798 VERTICAL-CHANNEL SEMICONDUCTOR DEVICE  
A vertical-channel semiconductor device having a buried bit line is disclosed. The vertical-channel semiconductor device enables an active pillar including a vertical channel region to be separate...
US20160104792 HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES  
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an...
US20160104774 NON-PLANAR VERTICAL DUAL SOURCE DRIFT METAL-OXIDE SEMICONDUCTOR (VDSMOS)  
A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure...
US20160104688 Robust and Reliable Power Semiconductor Package  
In one implementation, a semiconductor package includes a patterned conductive carrier including a support segment having a partially etched recess. The semiconductor package also includes an...
US20160099350 SEMICONDUCTOR DEVICE  
A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor...
US20160099328 METHOD OF FORMING NANOWIRES  
According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second nanowire over the substrate and...
US20160099307 TERMINATION DESIGN BY METAL STRAPPING GUARD RING TRENCHES SHORTED TO A BODY REGION TO SHRINK TERMINATION AREA  
This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active...
US20160099198 SEMICONDUCTOR PACKAGE APPARATUS  
A semiconductor package apparatus includes a lead frame, a first semiconductor chip, a second semiconductor chip, a first connecting element, and a second connecting element. The lead frame...
US20160093732 NON-FLOATING VERTICAL TRANSISTOR STRUCTURE  
A non-floating vertical transistor includes a substrate and a protuberant structure extending from the substrate. A segregating pillar is inside the protuberant structure. A pair of segregated...
US20160093612 HIGH VOLTAGE MULTIPLE CHANNEL LDMOS  
An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the...
US20160093611 SEMICONDUCTOR STRUCTURE WITH AN L-SHAPED BOTTOM PLATE  
A semiconductor structure having a first source/drain semiconductor structure connected to a vertical channel such that the source/drain semiconductor structure has a vertical side that is...
US20160093608 SEMICONDUCTOR DEVICE  
A semiconductor device is provided. The semiconductor device includes a first conductive portion on a first side of a first shallow trench isolation (STI) region. The first conductive portion is...
US20160087097 QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE AND METHOD OF FORMING THE SAME  
A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first...
US20160087059 Semiconductor Device and Method  
A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is utilized to help define a channel...
US20160087054 Self-Aligned Wrapped-Around Structure  
An vertical gate-all-around transistor and method of making is provided. The vertical gate-all-around transistor includes a first semiconductor structure extending above a substrate, and a gate...
US20160086968 SEMICONDUCTOR DEVICE  
A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of stack structures, and a plurality of support layers. The stack structures are disposed on the...
US20160079410 SEMICONDUCTOR DEVICE  
A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a...
US20160079275 THREE-DIMENSIONAL (3D) SEMICONDUCTOR DEVICE  
A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a...
US20160079229 SEMICONDUCTOR DEVICE  
A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second transistor on a second side of the...
US20160071931 METHOD OF FORMATION OF GERMANIUM NANOWIRES ON BULK SUBSTRATES  
A material stack comprising alternating layers of a silicon etch stop material and a germanium nanowire template material is formed on a surface of a bulk substrate. The material stack and a...
US20160071881 DOUBLE-SOURCE SEMICONDUCTOR DEVICE  
A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The...
US20160071874 INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME  
According to one embodiment, an integrated circuit device includes a substrate. The integrated circuit device also includes a stacked body provided on the substrate, insulating films and electrode...
US20160071864 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME  
According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked....
US20160064777 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE  
A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a...
US20160064557 VERTICAL JUNCTIONLESS TRANSISTOR DEVICE AND MANUFACTURING METHODS  
A method for forming a semiconductor device includes forming a fin device structure in a buffer layer on a substrate. The fin device structure includes a lower portion extending over the silicon...
US20160064547 Semiconductor Device with Field Electrode Structures in a Cell Area and Termination Structures in an Edge Area  
A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an...
US20160064542 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME  
The semiconductor device includes a semiconductor substrate, a plurality of source regions formed in a stripe shape on the semiconductor substrate, a plurality of gate electrodes formed in a...
US20160064541 VERTICAL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME  
A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel...
US20160064497 DEVICES, COMPONENTS AND METHODS COMBINING TRENCH FIELD PLATES WITH IMMOBILE ELECTROSTATIC CHARGE  
N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region...
US20160064478 SUPER-JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE THEREOF  
The present disclosure relates to a super-junction structure, a method for manufacturing the super-junction structure and a semiconductor device including the super-junction structure. The...
US20160056296 FIN FET AND METHOD OF FABRICATING SAME  
A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined...
US20160056281 EDGE TERMINATION FOR SUPER-JUNCTION MOSFETS  
Edge termination for super-junction MOSFETs. In accordance with an embodiment of the present invention, a super-junction metal oxide semiconductor field effect transistor (MOSFET) includes a core...
US20160056280 Minority Carrier Conversion Structure  
According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from...
US20160056276 TRANSISTOR STRUCTURE WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING IMMUNITY  
A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer...
US20160056248 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one...
US20160056175 Circuit Structures, Memory Circuitry, and Methods  
A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor...
US20160056137 SEMICONDUCTOR CHIP AND ELECTRONIC COMPONENT  
According to one embodiment, a semiconductor chip includes: a semiconductor layer; an upper electrode provided on the semiconductor layer; and a lower electrode provided under the semiconductor...
US20160056131 SEMICONDUCTOR DEVICE  
A primary surface of a normally-off field-effect transistor (102) on which a source electrode (120) is formed and a first primary surface of a die pad (105) are in contact with each other, and the...
US20160049472 VARIABLE CHANNEL STRAIN OF NANOWIRE TRANSISTORS TO IMPROVE DRIVE CURRENT  
A semiconductor device includes a nanowire structure and a stressor. The nanowire structure includes a first channel section and a second channel section. The stressor subjects the first channel...
US20160049466 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME  
To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a...
US20160049423 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the...
US20160049422 SEMICONDUCTOR DEVICE  
A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the insulating layer, the first and...
US20160049404 Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices  
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the...