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US20160254379 SEMICONDUCTOR DEVICE  
According to one embodiment, a semiconductor device includes a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second...
US20160247938 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first...
US20160247892 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a...
US20160247889 SEMICONDUCTOR DEVICE  
A semiconductor device includes first and second fin-shaped silicon layers on a substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. First and second...
US20160240667 Medium High Voltage MOSFET Device  
A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of...
US20160240666 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A device includes a first and a second semiconductor-layer. The second semiconductor-layer is on the first semiconductor-layer, and has a first and a second side-surface. A first gate-dielectric...
US20160240665 VERTICAL TRANSISTOR AND LOCAL INTERCONNECT STRUCTURE  
A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material...
US20160240626 Vertical Gate All Around (VGAA) Devices and Methods of Manufacturing the Same  
Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion...
US20160240623 VERTICAL GATE ALL AROUND (VGAA) DEVICES AND METHODS OF MANUFACTURING THE SAME  
Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion...
US20160240533 VERTICAL CMOS STRUCTURE AND METHOD  
A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g....
US20160240378 Vertical Gate All Around (VGAA) Devices and Methods of Manufacturing the Same  
Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first doped region having a first...
US20160233330 Gated Diode in a Press-Fit Housing and an Alternator Assembly Having a Gated Diode Arranged in a Load Path  
A gated diode in a press-fit housing includes a base configured to be press-fit into an opening of a diode carrier plate and including a pedestal portion with a first flat surface, and a head wire...
US20160233302 SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET UNIT INTERCONNECTING A SOURCE AND A DRAIN  
A semiconductor device includes a substrate, a pair of source/drain units, and a semiconductor sheet unit. The substrate includes a well region. The source/drain units are disposed above the well...
US20160225900 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME  
A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below...
US20160225895 NON-PLANAR SEMICONDUCTOR STRUCTURE WITH PRESERVED ISOLATION REGION  
A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a...
US20160225869 A POWER FIELD EFFECT TRANSISTOR, A POWER FIELD EFFECT TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING A POWER FIELD EFFECT TRANSISTOR  
A power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor are provided. During the manufacturing of the power field...
US20160211370 SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURE  
A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the...
US20160211369 Vertical Non-Planar Semiconductor Device for System-on-Chip (SoC) Applications  
Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor...
US20160211360 VERTICAL POWER TRANSISTOR DEVICE  
A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes...
US20160211259 Stacked Device and Associated Layout Structure  
Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate. A first source/drain region is...
US20160204251 PILLAR-SHAPED SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR  
A SiO2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the SiO2...
US20160204210 Semiconductor Device Having Field Plate Structures and Gate Electrode Structures Between the Field Plate Structures  
A semiconductor device includes a field effect transistor in a semiconductor substrate having a first surface. The field effect transistor includes a first field plate structure and a second field...
US20160204163 VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.
US20160204123 Method of fabricating three-dimensional semiconductor devices, and three-dimensional semiconductor devices thereof  
Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising providing a substrate and forming a plurality of layers over the...
US20160204115 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings...
US20160197181 SEMICONDUCTOR DEVICE WITH AN SGT AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device includes a P+ region and an N+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an i-layer substrate. Connections between a power...
US20160197179 SEMICONDUCTOR DEVICE  
In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the first conductive type. A power...
US20160190312 VERTICAL GATE ALL-AROUND TRANSISTOR  
Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to...
US20160181413 SEMICONDUCTOR DEVICE  
A semiconductor device is provided with an N−-type drift layer, a N+-type diffusion well region provided on a surface part of the N−-type drift layer, a P-type channel well region, an N+-type...
US20160181365 SEMICONDUCTOR DEVICES HAVING CHANNEL REGIONS WITH NON-UNIFORM EDGE  
A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed...
US20160181362 Silicide Regions in Vertical Gate All Around (VGAA) Devices and Methods of Forming Same  
An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the...
US20160172494 MEMORY CELL ARRAY AND CELL STRUCTURE THEREOF  
A memory device includes a substrate and a memory array. The substrate has a continuous active region. The memory array is disposed in the continuous active region of the substrate and includes a...
US20160163811 VERTICAL FIELD EFFECT TRANSISTORS  
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with...
US20160163810 GATE ALL AROUND DEVICE STRUCTURE AND FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE  
A gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device...
US20160163804 VERTICAL HIGH-VOLTAGE MOS TRANSISTOR AND METHOD OF FORMING THE MOS TRANSISTOR WITH IMPROVED ON-STATE RESISTANCE  
A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor...
US20160155857 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A semiconductor device includes first and second fin-shaped semiconductor layers on a substrate. First and second pillar-shaped semiconductor layers reside on the first and second fin-shaped...
US20160155842 PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME  
An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated...
US20160149028 SEMICONDUCTOR DEVICE WITH CHARGE COMPENSATION REGION UNDERNEATH GATE TRENCH  
A semiconductor substrate has a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped...
US20160149019 Semiconductor Device and Method  
Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped...
US20160148993 REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS  
An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact...
US20160141423 Contacts For Highly Scaled Transistors  
A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and...
US20160141416 SEMICONDUCTOR DEVICES AND FABRICATION METHODS  
Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first...
US20160141408 SUPER JUNCTION FIELD EFFECT TRANSISTOR WITH INTERNAL FLOATING RING  
A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of...
US20160141376 Vertical Semiconductor Device and Method for Manufacturing Therefor  
A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a...
US20160141365 GATE-ALL-AROUND FIN DEVICE  
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate....
US20160141362 OUTPUT CAPACITANCE REDUCTION IN POWER TRANSISTORS  
Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed...
US20160141356 SEMICONDUCTOR DEVICE  
A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type...
US20160133633 SRAM CELLS WITH VERTICAL GATE-ALL-ROUND MOSFETS  
A Static Random Access Memory (SRAM) cell includes a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second...
US20160126345 Semiconductor device and method for manufacturing the same  
A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas...
US20160126332 SEMICONDUCTOR DEVICE  
A semiconductor device includes a pillar-shaped silicon layer on a fin-shaped silicon layer. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a...