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US20110095371 Gate minimization threshold voltage of FET for synchronous rectification  
A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be...
US20070040191 Nanowire structures and electrical devices  
The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting...
US20120153359 NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION  
Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region...
US20070252175 Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions  
The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs...
US20110001169 FORMING UNIFORM SILICIDE ON 3D STRUCTURES  
By using a non-conformal diffusion barrier in conjunction with a similarly deposited non-conformal initial deposition of siliciding material, a substantially uniform and conformal silicide can be...
US20090166719 LDMOS SEMICONDUCTOR DEVICE MASK  
Embodiments relate to an LDMOS semiconductor device mask that may reduce current leakage under a gate-off condition. According to embodiments, an LDMOS semiconductor device mask may include a moat...
US20070210340 GaAs power transistor  
A GaAs power transistor unit cell is provided with one of its transistor contacts on its bottom surface, and its other two transistor contacts on its frontside surface. In one arrangement, the...
US20110062498 EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY  
Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments...
US20050161707 Esd-robust power switch and method of using same  
A power switch comprising a field effect transistor (FET) including an active area in a semiconductor body, a channel formed in said active area and having a periodic structure, source diffusion...
US20050184407 Transistor circuit, thin film transistor circuit and display device  
A TFT circuit includes a source terminal, a drain terminal, and first and second transistors having source-drain paths that are connected in series between the source terminal and the drain...
US20080012047 Two-terminal nanotube devices and systems and methods of making same  
A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first...
US20100042861 HOST, USB PORT MODULE, AND POWER MANAGEMENT METHOD THEREOF  
A universal serial bus (USB) port module for connecting an electronic apparatus with a USB is provided. The USB port module includes a USB controller and a detection circuit. The USB controller is...
US20120153358 INTEGRATED HEAT PILLAR FOR HOT REGION COOLING IN AN INTEGRATED CIRCUIT  
The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit...
US20080142849 Semiconductor ESD device and method of making same  
An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first...
US20070284623 Semiconductor device having vertical channel transistor  
A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar...
US20070090408 Narrow-body multiple-gate FET with dominant body transistor for high performance  
A field-effect transistor for a narrow-body, multiple-gate transistor such as a FinFET, tri-gate or Ω-FET is described. The corners of the channel region disposed beneath the gate are rounded n,...
US20060046491 CMP polishing method and method for manufacturing semiconductor device  
A wafer substrate having a wiring pattern formed between materials with a dielectric constant of 2 or less is polished with the polishing pressure being set at 0.01 to 0.2 psi. As a result,...
US20110132439 FULLERENE COMPOUNDS FOR SOLAR CELLS AND PHOTODETECTORS  
Amorphous fullerene derivatives and their use in organic electronic devices that include the fullerene derivative as the electron acceptor component in the device's active layer.
US20100078651 ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE  
Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has...
US20070090409 Semiconductor device comprising an undoped oxide barrier  
The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the...
US20100230727 Electric Circuit with Vertical Contacts  
An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different...
US20060265789 Nanotube with a T shaped structure and a field effect transistor, and a method of manufacturing the same  
To realize a transistor with a channel and a gate, both being formed with nanotubes, by joining the nanotubes in the form of SP3 bonding, a substrate, on which a pair of source and drain...
US20050040437 Cascaded transistors in one well  
A semiconductor device for reducing the chip-area on an integrated circuit required for multiple, cascaded MOS transistors, a method of designing said devices and an exemplary portions of circuits...
US20090236603 PROCESS FOR FORMING A WIRING FILM, A TRANSISTOR, AND AN ELECTRONIC DEVICE  
A wiring film having excellent adhesion and a low resistance is formed. A barrier film having copper as a main component and containing oxygen is formed on an object to form a film thereon by...
US20080283874 Field-Effect Transistors  
The present invention provides a field-effect transistor and method for the fabrication of a field-effect transistor by deposition on a substrate (480), which method comprises a wet chemical...
US20080079029 Multi-terminal electrically actuated switch  
A multi-terminal electrically actuated switch comprises a source electrode, a drain electrode, and an active region physically connected to both electrodes. The active region comprises at least...
US20090184322 ELECTROCONDUCTIVE FILM-FORMING METHOD, A THIN FILM TRANSISTOR, A THIN FILM TRANSISTOR-PROVIDED PANEL AND A THIN FILM TRANSISTOR-PRODUCING METHOD  
An electroconductive film having high adhesion and a low resistivity is formed. An electroconductive film composed mainly of copper and containing an addition metal such as Ti is formed by...
US20050116360 Complementary field-effect transistors and methods of manufacture  
A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a <100> crystal orientation. Tensile stress, which increases...
US20130234213 NISI REWORK PROCEDURE TO REMOVE PLATINUM RESIDUALS  
The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected....
US20060237750 Field effect transistor structures  
An embodiment of the present invention provides a structure comprising a field effect transistor (FET) comprising: at least one source rail with at least one source finger; at least one drain rail...
US20070205436 Flash memory cell with split gate structure and method for forming the same  
A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is...
US20050116257 Field effect transister structures  
A structure comprising a field effect transistor (FET) comprising at least one source rail with at least one source finger, at least one drain rail with at least one drain finger, and at least one...
US20060006554 Vertical structure semiconductor devices with improved light output  
The invention provides a reliable technique to fabricate a new vertical structure compound semiconductor devices with highly improved light output. An exemplary embodiment of a method of...
US20060049428 Tft electronic devices and their manufacture  
An electronic device (70) comprises a thin film transistor (TFT) (9,59), the TFT including a channel (16) defined in a layer of polycrystalline semiconductor material (10,48). The polycrystalline...
US20070210339 Shared contact structures for integrated circuits  
In one embodiment, a shared contact structure electrically connects a gate, a diffusion region, and another diffusion region. The shared contact structure may comprise a trench that exposes the...
US20060197112 Optical Coupling Device  
In various aspects, an optical coupling device may include a light emitting element configured to emit an optical signal; a photo receiving element having a serial connected of photo diodes, the...
US20070158693 DEVICE OF ACTIVE REGIONS AND GATES AND METHOD OF FORMING GATE PATTERNS USING THE SAME  
A semiconductor device having an improved gate process margin includes two active regions spaced apart from each other on a semiconductor substrate and respectively having bent sides with recesses...
US20090174428 PROGRAMMABLE ELEMENT, AND MEMORY DEVICE OR LOGIC CIRCUIT  
A multi-terminal programmable element. The programmable element includes a source electrode and a drain electrode on a base. The programmable element includes reference voltage contact that is not...
US20090184343 ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME  
A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop...
US20050258455 Semiconductor component  
A semiconductor component has a first and a second contact-making region, and a semiconductor volume arranged between the first and the second contact-making region. Within the semiconductor...
US20060125121 Capacitor-less 1T-DRAM cell with Schottky source and drain  
A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor...
US20080006850 System and method for forming through wafer vias using reverse pulse plating  
A method for forming through wafer vias in a substrate uses a Cr/Au seed layer to plate the bottom of a blind trench formed in the front side of a substrate. Thereafter, a reverse plating process...
US20090135229 ELEMENT SUBSTRATE, PRINTHEAD, AND HEAD CARTRIDGE  
This invention provides an element substrate having a heater selection circuit normally operable even in the use of voltage conversion circuits, which are arranged along the nozzle arrayed...
US20070252176 FIELD EFFECT TRANSISTOR FOR DETECTING IONIC MATERIAL AND METHOD OF DETECTING IONIC MATERIAL USING THE SAME  
A field effect transistor for detecting ionic material and a method of detecting ionic material using the field effect transistor. The field effect transistor for detecting ionic material includes...
US20080099757 Organic field effect transistor and semiconductor device  
It is an object to provide an organic field effect transistor including an electrode which can reduce an energy barrier at an interface between a conductive layer and a semiconductor layer, and a...
US20070029577 Field effect transistor and method of manufacturing the same  
A field effect transistor includes a first semiconductor region of a first conduction type, a gate electrode formed on the channel region of the first semiconductor region via a gate insulating...
US20060157741 Semiconductor device including gate insulation film that is formed of pyroceramics, and method of manufacturing the same  
A semiconductor device includes a gate insulation film that is formed of pyroceramics including an amorphous matrix layer, which is provided on a major surface of a silicon substrate, and...
US20080185615 Method and Apparatus for Double-Sided Biasing of Nonvolatile Memory  
Methods and apparatuses are disclosed for biasing the source-side and the drain-side of a nonvolatile memory to add electrons to the charge trapping structure.
US20050274985 RF decoupled field plate for FETs  
A field effect transistor structure having a field effect transistor; a field plate disposed between a gate electrode of the transistor and a drain electrode of the transistor; and a resistive...
US20080173901 CMOS DEVICES HAVING CHANNEL REGIONS WITH A V-SHAPED TRENCH AND HYBRID CHANNEL ORIENTATIONS, AND METHOD FOR FORMING THE SAME  
The present invention relates to a field effect transistor (FET) containing a channel extending perpendicularly across at least one V-shaped trench and along the interior surfaces thereof. In one...

Matches 1 - 50 out of 128 1 2 3 >